128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

shrink-TSOP KM416S8030BN Preliminary CMOS SDRAM 128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL www.DataSheet4U.com Revision 0.1 Aug. 1999 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Aug. 1999 shrink-TSOP KM416S8030BN Revision History Version 0.0 (July 2, 1999, Preliminary) • Preliminary specification for shrink-TSOP. Preliminary CMOS SDRAM Version 0.1 (August 24, 1999, Preliminary) • Added Note 5 in OPERATING AC PARAMETER. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported. • SAMSUNG recommends tRDL=2CLK and tDAL=2CLK+20ns. Rev. 0.1 Aug. 1999 shrink-TSOP KM416S8030BN Preliminary CMOS SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM in New Shrink-TSOP(sTSOP) FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) GENERAL DESCRIPTION The KM416S8030B is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part No. KM416S8030BN-G/FL Max Freq. 100MHz(CL=3) Interface Package LVTTL 54pin sTSOP(II) KM416S8030BN-G/FH 100MHz(CL=2) FUNCTIONAL BLOCK DIAGRAM I/O Control LWE Data Input Register LDQM Bank Select 2M x 16 2M x 16 2M x 16 2M x 16 Refresh Counter Output Buffer Row Decoder Sense AMP Row Buffer DQi Address Register CLK ADD Column Decoder Col. Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Programming Register LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE LDQM UDQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Aug. 1999 shrink-TSOP KM416S8030BN PIN CONFIGURATION (Top view) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Preliminary CMOS SDRAM 54Pin sTSOP (400mil x 441mil) (0.4 mm Pin pitch) VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS PIN FUNCTION DESCRIPTION Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. CKE Clock enable A0 ~ A11 BA0 ~ BA1 RAS CAS WE L(U)DQM DQ0 ~ 15 Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use VDD/VSS VDDQ/VSSQ N.C/RFU Rev. 0.1 Aug. 1999 shrink-TSOP KM416S8030BN ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Preliminary CMOS SDRAM Unit V V °C W mA Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ, Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE Clock (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4.0 5.0 5.0 6.5 Unit pF pF pF pF Note 1 2 2 3 RAS, CAS, WE, CS, CKE, DQM Address DQ0 ~ DQ15 Rev. 0.1 Aug. 1999 shrink-TSOP KM416S8030BN DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns Test Condition Preliminary CMOS SDRAM Version -H -L 140 1 1 20 Unit Note Operating current (One bank active) Precharge standby current in power-down mode ICC1 ICC2P mA 1 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable mA Precharge standby current in non power-down mode ICC2NS mA 7 5 5 30 20 mA mA Active standby current in power- ICC3P CKE ≤ VIL(max), tCC = 10ns down mode ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ Active standby current in non power-down mode (One bank active) ICC3N ICC3NS CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V G F Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. KM416S8030BN-G** 4. KM416S8030BN-F** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ) mA Operating current (Burst mode) Refresh current Self refresh current ICC4 145 mA 1 ICC5 ICC6 210 1.5 800 mA mA uA 2 3 4 Rev. 0.1 Aug. 1999 shrink-TSOP KM416S8030BN AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V Preliminary CMOS SDRAM Unit V V ns V Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 Vtt = 1.4V 1200Ω Output 870Ω 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50Ω 50Ω 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol -H tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 20 20 20 50 100 70 2 2 CLK + 20 ns 1 1 1 2 1 Version -L ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. tRDL=1CLK and tDAL=1CLK+20ns is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns. Rev. 0.1 Aug. 1999 shrink-TSOP KM416S8030BN AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS latency=3 CAS latency=2 CLK to valid output delay Output data hold time CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 3 3 2 1 1 6 6 tSAC Symbol Min CLK cycle time tCC 10 10 6 6 3 3 3 3 2 1 1 6 7 -H Max 1000 Min 10 12 6 7 -L Max 1000 Preliminary CMOS SDRAM Unit Note ns 1 ns 1,2 ns ns ns ns ns ns ns 2 3 3 3 3 2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. I