Flash Memory

www.DataSheet4U.com KM29N040T, KM29N040IT Document Title 512K x 8 Bit NAND Flash Memory FLASH MEMORY Revision History Revision No. History 0.0 1.0 1.1 Data Sheet 1997. Data Sheet 1998. Data Sheet 1998. Draft Date April 10th 1997 April 10th 1998 July 14th 1998 Remark Final The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to cha nge the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questio ns, please contact the SAMSUNG branch office near you. 1 www.DataSheet4U.com KM29N040T, KM29N040IT 512K x 8 Bit NAND Flash Memory FEATURES • Single 5.0 - volt Power Supply • Organization - Memory Cell Array : 512K x 8 - Data Register : 32 x 8 bit • Automatic Program and Erase - Frame Program : 32Byte in 500 µs - Block Erase : 4K Byte in 6ms • 32-Byte Frame Read Operation - Random Access : 15 µs(Max.) - Serial Frame Access : 120ns(Min.) • Command/Address/Data Multiplexed I/O port • Low Operation Current (Typical) - 10µA Standby Current - 10mA Read/ Program/Erase Current • Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles • 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch) FLASH MEMORY GENERAL DESCRIPTION The KM29N040 is a 512Kx8bit NAND Flash Memory. Its NAND cell structure provides the most cost-effective solution for Digital Audio Recording. A Program operation programs a 32-byte frame in typically 500 µs and an Erase operation erase a 4Kbyte block in typically 6ms. Data in a frame can be read out at a burst cycle rate of 120ns/byte. The I/O pins serve as the ports for address and data input/output as well as for command inputs. The on-chip write controller automates the Program and Erase operations, including Program or Erase pulse repetition, where required, and performs internal verification of cell data. The KM29N040 is an optimum solution for flash memory application that do not require the high performance levels or capacity of larger density flash memories. These application include data storage in digital Telephone Answering Devices(TAD) and other consumer applications that require voice data storage. PIN CONFIGURATION PIN DESCRIPTION Pin Name I/O0 ~ I/O7 CLE Pin Function Data Inputs/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Ground Input Ready/Busy output Power Ground No Connection VSS CLE ALE WE WP N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC CE RE R/B GND N.C N.C N.C N.C N.C ALE CE RE WE WP GND R/B VCC VSS N.C N.C N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 VCC 44(40) TSOP (II) NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC, VSS or GND inputs disconnected. 2 www.DataSheet4U.com KM29N040T, KM29N040IT Figure 1. FUNCTIONAL BLOCK DIAGRAM FLASH MEMORY A7 - A18 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders 4M Bit NAND Flash ARRAY 32Byte x 4frame x 4096row A0 - A6 Page Register & S/A Command Command Register Y-Gating I/O Buffers & Latches CE RE WE Control Logic & High Voltage Generator I/O0 Global Buffers I/O7 CLE ALE WP Figure 2. ARRAY ORGANIZATION Good Block 1Block(32Row) (4K Byte) The 1st Blockt(4KB) The 1st Block (4KB) 4M : 4K Row (=128 Blocks) 1 Frame = 32 Byte 1 Row = 4 Frames = 128 Bytes 1 Block = 32 rows = 4K Bytes 1 Device = 32B x 4frames x 32rows x 128blocks = 4Mbits 8bit 128Byte Column 1 2 3 4 Frame Register 32 Byte I/O0 ~ I/O7 I/O0 1st Cycle 2nd Cycle 3rd Cycle A0 A8 A16 I/O1 A1 A9 A17 I/O2 A2 A10 A18 I/O3 A3 A11 X* I/O4 A4 A12 (1) I/O5 A5 A13 X* I/O6 A6 A14 *X I/O7 A7 A15 *X Column Address (A0-A4) Frame Address (A5-A6) Row Address (A7-A11) Block Address (A12-A18) X* NOTE : *(1) : X can be VIL or VIH 3 www.DataSheet4U.com KM29N040T, KM29N040IT PRODUCT INTRODUCTION FLASH MEMORY The KM29N040 is a 4M bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The memory array is composed of unit NAND structures in which 8 cells are connected serially. Each of the 8 cells reside in a different row. A block consists of the 32 rows, totaling 4096 NAND structures of 8bits each. The array organization is shown in Figure 2. The program and read operations are executed on a frame basis, while the erase operation is e xecuted on a block basis. The memory array consists of 128 separately erasable 4K-byte blocks. The KM29N040 has addresses multiplexed into 8 I/O pins. This scheme not only reduces pin count but allows systems upgrades to higher density flash memories by maintaining consistency in system board design. Command, address and data are all written through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except for Block Erase command which requires two cycles. For byte-level addressing, the 512K byte physical space requires a 19-bit address, low row address and high row address. Frame Read and frame Program require the same three address cycles following by a command input. In the Block Erase operation, however, only the two row address cycles are required. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the KM29N040. Table 1. COMMAND SETS Function Read Reset Frame Program Block Erase Status read Read ID 1st. Cycle 00h FFh 80h 60h 70h 90h 2nd. Cycle 10h D0h O O Acceptable Command during Busy 4 www.DataSheet4U.com KM29N040T, KM29N040IT PIN DESCRIPTION Command Latch Enable(CLE) FLASH MEMORY The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the path activation for address and input data to the internal address/data register. Addresses are latch ed on the rising edge of WE with ALE high, and input data is latched when ALE is low. Chip Enable(CE) The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode. However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby mode. Write Enable( WE) The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. Read Enable( RE) The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t of RE which also increments the internal column address counter by one. REA after the falling edge I/O Port : I/O 0 ~ I/O7 The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high- z when the chip is deselected or when the outputs are disabled. Write Protect( WP) The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. Ready/Busy(R/B) The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. 5 www.DataSheet4U.com KM29N040T, KM29N040IT ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to V SS Temperature Under Bias Storage Temperature Short Circuit Output Current KM29N040T KM29N040IT TSTG IOS Symbol VIN TBIAS FLASH MEMORY Rating -0.6 to +7.0 -10 to +125 -40 to +125 -65 to +150 5 Unit V °C °C mA NOTE: 1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, KM29N040T:TA=0 to 70°C, KM29N040IT:TA=-40 to 85°C) Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 4.5 0 Typ. 5.0 0 Max 5.5 0 Unit V V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.) Parameter Burst Read Cycle Operating Current Command, Address Input Data Input Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All inputs Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/ B) Symbol ICC1 ICC3 ICC4 ICC5 ICC6 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOL(R/B) IOH=-400µA IOL=2.1mA VOL=0.4V Test Conditions tcycle=120ns tcycle=120ns tcycle=120ns CE=VIH, WP=0V/VCC CE=VCC-0.2, WP=0V/VCC VIN=0 to 5.5V VOUT=0 to 5.5V CE=VIL, IOUT=0mA Min 2.4 -0.3 2.4 8 Typ 10 10 10 10 10 10 10 Max 20 20 20 20 20 1 50 ±10 ±10 VCC+0.5 0.8 0.4 mA V µA mA Unit 6 www.DataSheet4U.com KM29N040T, KM29N040IT VALID BLOCK Parameter Valid Block Number Symbol NVB Min 125 Typ. - FLASH MEMORY Max 128 Unit Block NOTE : 1. The KM29N040 may or may not include bad blocks. Bad blocks are defined as blocks that contain one or more