(K9XXG08UXM) Flash Memory

www.DataSheet4U.com K9LAG08U1M K9G8G08U0M Preliminary FLASH MEMORY K9XXG08UXM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 www.DataSheet4U.com K9LAG08U1M K9G8G08U0M Preliminary FLASH MEMORY Document Title 1G x 8 Bit / 2G x 8 Bit NAND Flash Memory Revision History Revision No 0.0 0.1 0.2 History Draft Date Remark Advance Advance Advance 1. Initial issue Feb. 1st 2005 1. Cycle time is changed from 35ns to 30ns Apr. 1st 2005 2. Technical note is changed. 1. AC Para. tRHW deleted Sept. 1. 2005 2. the power recovery time of minmum is changed from 10µs to 100µs(p38) 1. Leaded part is eliminated. 2. tR 50us -> 60us (p. 3,12,31) 3. tRHW, tCSD parameter is defined. 4. Technical note is added.(p.16) 1. Endurance is changed (10K->5K) 1. Max. tPROG is changed (2ms->3ms) 1. Address scramble is added (p.33) 2. Program/Erase Characteristics Note 3 is added(p.11) Mar. 20th. 2006 0.3 Advance 0.4 0.5 0.6 Apr. 20th 2006 Apr. 25th 2006 June 30th 2006 Advance Advance Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. 2 www.DataSheet4U.com K9LAG08U1M K9G8G08U0M Preliminary FLASH MEMORY 1G x 8 Bit / 2G x 8 Bit NAND Flash Memory PRODUCT LIST Part Number K9G8G08U0M-P K9G8G08U0M-I K9LAG08U1M-I 2.7V ~ 3.6V X8 Vcc Range Organization PKG Type TSOP1 52ULGA FEATURES • Voltage Supply : 2.7 V ~ 3.6 V • Organization - Memory Cell Array : (1G + 32M)bit x 8bit - Data Register : (2K + 64)bit x8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (256K + 8K)Byte • Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 60µs(Max.) - Serial Access : 30ns(Min.) • Memory Cell : 2bit / Memory Cell • Fast Write Cycle Time - Program time : 800µs(Typ.) - Block Erase Time : 1.5ms(Typ.) • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology - Endurance : 5K Program/Erase Cycles(with 4bit/512byte ECC) - Data Retention : 10 Years • Command Register Operation • Unique ID for Copyright Protection • Package : - K9G8G08U0M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9G8G08U0M-ICB0/IIB0 52 - Pin ULGA (12 x 17 / 1.00 mm pitch) - K9LAG08U1M-ICB0/IIB0 52 - Pin ULGA (12 x 17 / 1.00 mm pitch) GENERAL DESCRIPTION Offered in 1Gx8bit, the K9G8G08U0M is a 8G-bit NAND Flash Memory with spare 256M-bit. Its NAND cell provides the most costeffective solution for the solid state mass storage market. A program operation can be performed in typical 800µs on the 2,112-byte page and an erase operation can be performed in typical 1.5ms on a (256K+8K)byte block. Data in the data register can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9G8G08U0M′s extended reliability of 5K program/ erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9G8G08U0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. 3 www.DataSheet4U.com K9LAG08U1M K9G8G08U0M PIN CONFIGURATION (TSOP1) K9G8G08U0M-PCB0/PIB0 N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C Preliminary FLASH MEMORY 48-pin TSOP1 Standard Type 12mm x 20mm PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220AF Unit :mm/Inch 0.10 MAX 0.004 #48 ( 0.25 ) 0.010 12.40 0.488 MAX #24 #25 1.00±0.05 0.039±0.002 0.25 0.010 TYP +0.075 20.00±0.20 0.787±0.008 0.20 -0.03 +0.07 #1 0.008-0.001 0.16 -0.03 +0.07 +0.003 0.50 0.0197 12.00 0.472 0.05 0.002 MIN 0.125 0.035 0~8° 0.45~0.75 0.018~0.030 ( 0.50 ) 0.020 4 +0.003 0.005-0.001 18.40±0.10 0.724±0.004 1.20 0.047MAX www.DataSheet4U.com K9LAG08U1M K9G8G08U0M PIN CONFIGURATION (ULGA) K9G8G08U0M-ICB0/IIB0 A NC Preliminary FLASH MEMORY B NC C D E NC F G H J K NC L M N NC NC 7 NC /RE Vcc /CE NC NC Vss NC ALE NC NC NC NC R/B NC Vss NC IO0 /WP NC IO1 NC NC NC IO7 IO6 IO2 IO3 NC NC NC IO5 IO4 Vss Vss NC NC NC Vcc NC NC NC 6 5 4 3 2 1 NC NC CLE /WE PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View Bottom View 12.00±0.10 10.00 1.00 1.00 6 5 4 3 2 1.00 1 1.30 A B 2.00 12.00±0.10 7 (Datum A) #A1 1.00 A B C D (Datum B) 1.00 2.50 12-∅1.00±0.05 ∅0.1 M C AB 17.00±0.10 F G J K L M N 1.00 H 41-∅0.70±0.05 ∅0.1 M C AB 17.00±0.10 0.10 C 5 0.65(Max.) Side View 0.50 2.00 1.00 2.50 12.00 17.00±0.10 E www.DataSheet4U.com K9LAG08U1M K9G8G08U0M Preliminary FLASH MEMORY K9LAG08U1M-ICB0/IIB0 A NC B NC C D E NC F G H J K NC L M N NC NC 7 NC /RE1 Vcc /CE1 /CE2 CLE2 /RE2 R/B1 R/B2 Vss /WP2 IO0-1 IO7-2 IO6-2 IO5-2 Vcc IO4-2 IO3-2 Vss IO2-2 NC NC NC NC 6 5 4 3 2 1 NC NC IO7-1 IO6-1 IO5-1 IO4-1 Vss CLE1 Vss /WE1 /WP1 IO2-1 IO3-1 ALE2 ALE1 IO1-1 IO0-2 /WE2 NC IO1-2 NC NC PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View Bottom View 12.00±0.10 10.00 1.00 1.00 6 5 4 3 2 1.00 1 1.30 A B 2.00 12.00±0.10 7 (Datum A) #A1 1.00 A B C D (Datum B) 1.00 2.50 12-∅1.00±0.05 ∅0.1 M C AB 17.00±0.10 F G J K L M N 1.00 H 41-∅0.70±0.05 ∅0.1 M C AB 17.00±0.10 0.10 C 6 0.65(Max.) Side View 0.50 2.00 1.00 2.50 12.00 17.00±0.10 E www.DataSheet4U.com K9LAG08U1M K9G8G08U0M PIN DESCRIPTION Pin Name I/O0 ~ I/O7 Pin Function Preliminary FLASH MEMORY DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE control during read operation, refer to ’Page read’ section of Device operation. READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. POWER VCC is the power supply for device. GROUND NO CONNECTION Lead is not internally connected. CLE ALE CE RE WE WP R/B Vcc Vss N.C NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. 7 www.DataSheet4U.com K9LAG08U1M K9G8G08U0M Figure 1-1. K9G8G08U0M Functional Block Diagram VCC VSS A12 - A30 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders 8,192M + 256M Bit NAND Flash ARRAY Preliminary FLASH MEMORY A0 - A11 (2,048 + 64)Byte x 524,288 Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS Output Driver I/0 0 CE RE WE Control Logic & High Voltage Generator Global Buffers I/0 7 CLE ALE WP Figure 2-1. K9G8G08U0M Array Organization 1 Block = 128 Pages (256K + 8k) Byte 512K Pages (=4,096 Blocks) 8 bit 2K Bytes 64 Bytes 1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 128 Pages = (256K + 8K) Bytes 1 Device = (2K+64)B x 128Pages x 4,096 Blocks = 8,448 Mbits Page Register 2K Bytes I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle A0