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K4T1G044QQ K4T1G084QQ K4T1G164QQ DDR2 SDRAM 1Gb Q-die DDR2 SDRAM Specification www.DataSheet4U.com 60FBGA & 84FBGA with Pb-Free & Halogen-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 of 44 Rev. 1.01 November 2007 K4T1G044QQ K4T1G084QQ K4T1G164QQ DDR2 SDRAM Table of Contents 1.0 Ordering Information ................................................................................................................... 4 2.0 Key Features ................................................................................................................................ 4 3.0 Package Pinout/Mechanical Dimension & Addressing ............................................................ 5 3.1 x4/x8 package pinout (Top View) : 60ball FBGA Package ................................................................... 5 3.2 x16 package pinout (Top View) : 84ball FBGA Package ...................................................................... 6 3.3 FBGA Package Dimension (x4/x8) ................................................................................................... 7 3.4 FBGA Package Dimension (x16) ...................................................................................................... 8 4.0 Input/Output Functional Description ......................................................................................... 9 www.DataSheet4U.com 5.0 DDR2 SDRAM Addressing ........................................................................................................ 10 6.0 Absolute Maximum DC Ratings ................................................................................................ 11 7.0 AC & DC Operating Conditions ................................................................................................ 11 7.1 Recommended DC Operating Conditions (SSTL - 1.8) ...................................................................... 11 7.2 Operating Temperature Condition ................................................................................................. 12 7.3 Input DC Logic Level ................................................................................................................... 12 7.4 Input AC Logic Level ................................................................................................................... 12 7.5 AC Input Test Conditions ............................................................................................................. 12 7.6 Differential input AC logic Level .................................................................................................... 13 7.7 Differential AC output parameters ................................................................................................. 13 8.0 ODT DC electrical characteristics ............................................................................................ 13 9.0 OCD default characteristics ...................................................................................................... 14 10.0 IDD Specification Parameters and Test Conditions ............................................................. 15 11.0 DDR2 SDRAM IDD Spec Table ................................................................................................ 17 12.0 Input/Output capacitance ........................................................................................................ 18 13.0 Electrical Characteristics & AC Timing for DDR2-800/667.................................................... 18 13.1 Refresh Parameters by Device Density ......................................................................................... 18 13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .............................................. 18 13.3 Timing Parameters by Speed Grade ............................................................................................. 19 14.0 General notes, which may apply for all AC parameters ....................................................... 21 15.0 Specific Notes for dedicated AC parameters ........................................................................ 23 2 of 44 Rev. 1.01 November 2007 K4T1G044QQ K4T1G084QQ K4T1G164QQ DDR2 SDRAM Year 2007 2007 - Initial Release - Typo Correction History Revision History Revision 1.0 1.01 Month September November www.DataSheet4U.com 3 of 44 Rev. 1.01 November 2007 K4T1G044QQ K4T1G084QQ K4T1G164QQ 1.0 Ordering Information Org. 256Mx4 128Mx8 64Mx16 DDR2-800 5-5-5 K4T1G044QQ-HC(L)E7 K4T1G084QQ-HC(L)E7 K4T1G164QQ-HC(L)E7 DDR2-800 6-6-6 K4T1G044QQ-HC(L)F7 K4T1G084QQ-HC(L)F7 K4T1G164QQ-HC(L)F7 DDR2-667 5-5-5 DDR2 SDRAM Package 60 FBGA 60 FBGA 84 FBGA K4T1G044QQ-HC(L)E6 K4T1G084QQ-HC(L)E6 K4T1G164QQ-HC(L)E6 Note : 1. Speed bin is in order of CL-tRCD-tRP. 2. RoHS Compliant. 3. “H” of Part number(12th digit) stand for RoHS compliant and Halogen-free products. 2.0 Key Features Speed www.DataSheet4U.com CAS Latency tRCD(min) tRP(min) tRC(min) DDR2-800 5-5-5 5 12.5 12.5 57.5 DDR2-800 6-6-6 6 15 15 60 DDR2-667 5-5-5 5 15 15 60 Units tCK ns ns ns • JEDEC standard 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/ pin • 8 Banks • Posted CAS • Programmable CAS Latency: 3, 4, 5, 6 • Programmable Additive Latency: 0, 1, 2, 3, 4, 5 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended datastrobe is an optional feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination • Special Function Support - PASR(Partial Array Self Refresh) - 50ohm ODT - High Temperature Self-Refresh rate enable • Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C • All of Lead-free products are compliant for RoHS The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchronous device achieves high speed doubledata-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/ CAS multiplexing style. For example, 1Gb(x8) device receive 14/ 10/3 addressing. The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ. The 1Gb DDR2 device is available in 60ball FBGAs(x4/x8) and in 84ball FBGAs(x16). Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device Operation & Timing Diagram”. 4 of 44 Rev. 1.01 November 2007 K4T1G044QQ K4T1G084QQ K4T1G164QQ 3.0 Package Pinout/Mechanical Dimension & Addressing 3.1 x4/x8 package pinout (Top View) : 60ball FBGA Package 1 VDD DQ6 VDDQ DDR2 SDRAM 2 NU/ RDQS 3 VSS DM/ RDQS 7 A B C D E F G H J K L VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC 8 DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 A13 9 VDDQ DQ7 VDDQ DQ5 VDD ODT VSSQ DQ1 VSSQ VREF CKE VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC www.DataSheet4U.com DQ4 VDDL BA2 BA0 A10/AP VDD VSS A3 A7 VSS VDD A12 Note: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input masking function is disabled. 3. The function of DM or RDQS/RDQS are enabled by EMRS command. 4. VDDL and VSSDL are power and ground for the DLL. Ball Locations (x4/x8) 1 A B C D E F G H J K L 2 : Populated Ball + : Depopulated Ball Top View (See the balls through the Package) 3 4 5 6 7 8 9 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 5 of 44 Rev. 1.01 November 2007 K4T1G044QQ K4T1G084QQ K4T1G164QQ DDR2 SDRAM 3.2 x16 package pinout (Top View) : 84ball FBGA Package 1 VDD DQ14 VDDQ DQ12 VDD DQ6 2 NC VSSQ DQ9 VSSQ NC VSSQ DQ1 VSSQ VREF CKE 3 VSS UDM VDDQ DQ11 VSS LDM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC 7 A B C D E F G H J K L M N P R VSSQ UDQS VDDQ DQ10 VSSQ LDQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC 8 UDQS VSSQ DQ8 VSSQ LDQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 NC 9 VDDQ DQ15 VDDQ DQ13 VDDQ DQ7 VDDQ DQ5 VDD ODT www.DataSheet4U.com VDDQ DQ4 VDDL BA2 BA0 A10/AP VDD VSS A3 A7 VSS VDD A12 Note : 1. VDDL and VSSDL are power and ground for the DLL.

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