(K4S28xx32I) JEDEC standard 3.3V power supply LVTTL compatible

K4S280432I www.DataSheet4U.com K4S280832I K4S281632I Synchronous DRAM 128Mb I-die SDRAM Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 of 14 Rev. 1.1 May 2006 K4S280432I www.DataSheet4U.com K4S280832I K4S281632I Synchronous DRAM Year 2005 2006 - Final spec release. - Added 5ns speed bin for x16 History Revision History Revision 1.0 1.1 Month October May 2 of 14 Rev. 1.1 May 2006 K4S280432I www.DataSheet4U.com K4S280832I K4S281632I Synchronous DRAM 8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM FEATURES • • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh • 64ms refresh period (4K Cycle) • RoHS compliant for Pb-free Package GENERAL DESCRIPTION The K4S280432I / K4S280832I / K4S281632I is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Ordering Information Part No. K4S280432I-T(U)C/L75 K4S280832I-T(U)C/L75 K4S281632I-T(U)C/L50 K4S281632I-T(U)C/L60 K4S281632I-T(U)C/L75 Orgainization 32Mb x 4 16Mb x 8 8Mb x 16 8Mb x 16 8Mb x 16 Max Freq. 133MHz (CL=3) 133MHz (CL=3) 200MHz (CL=3) 166MHz (CL=3) 133MHz (CL=3) LVTTL 54pin TSOP(II) Interface Package Organization 32Mx4 16Mx8 8Mx16 Row Address A0~A11 A0~A11 A0~A11 Column Address A0-A9, A11 A0-A9 A0-A8 Row & Column address configuration 3 of 14 Rev. 1.1 May 2006 K4S280432I www.DataSheet4U.com K4S280832I K4S281632I Package Physical Dimension Synchronous DRAM 0~8°C 0.25 TYP 0.010 #54 #28 0.45~0.75 0.018~0.030 0.05 MIN 0.002 11.76±0.20 0.463±0.008 22.62 MAX 0.891 22.22 0.875 0.10 MAX 0.004 ( ± 0.10 ± 0.004 0.125+0.075 -0.035 0.005+0.003 -0.001 0.21 0.008 ± 0.05 ± 0.002 1.00 0.039 ± 0.10 ± 0.004 1.20 MAX 0.047 0.71 ) 0.028 0.30 -0.05 0.012 +0.004 -0.002 +0.10 0.80 0.0315 54Pin TSOP(II) Package Dimension 4 of 14 Rev. 1.1 May 2006 ( 0.50 ) 0.020 #1 #27 10.16 0.400 K4S280432I www.DataSheet4U.com K4S280832I K4S281632I FUNCTIONAL BLOCK DIAGRAM Synchronous DRAM I/O Control LWE LDQM Data Input Register Bank Select 8M x 4 / 4M x 8 / 2M x 16 Sense AMP 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register CLK ADD Column Decoder Col. Buffer Latency & Burst Length Programming Register LRAS LCBR LCKE LRAS LCBR LWE LCAS Timing Register LWCBR LDQM CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. 5 of 14 Rev. 1.1 May 2006 K4S280432I www.DataSheet4U.com K4S280832I K4S281632I PIN CONFIGURATION (Top view) x16 x8 x4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Synchronous DRAM x4 VSS N.C VSSQ N.C DQ3 VDDQ N.C N.C VSSQ N.C DQ2 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS x8 VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS VDD VDD VDD DQ0 DQ0 N.C VDDQ VDDQ VDDQ DQ1 N.C N.C DQ2 DQ1 DQ0 VSSQ VSSQ VSSQ DQ3 N.C N.C DQ4 DQ2 N.C VDDQ VDDQ VDDQ DQ5 N.C N.C DQ6 DQ3 DQ1 VSSQ VSSQ VSSQ DQ7 N.C N.C VDD VDD VDD LDQM N.C N.C WE WE WE CAS CAS CAS RAS RAS RAS CS CS CS BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD 54Pin TSOP (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin CLK CS CKE Name System clock Chip select Clock enable Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. (x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15) Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM DQ0 ~ N VDD/VSS VDDQ/VSSQ N.C/RFU Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use 6 of 14 Rev. 1.1 May 2006 K4S280432I www.DataSheet4U.com K4S280832I K4S281632I ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Synchronous DRAM Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V °C W mA Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE Clock (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 3.5 3.8 3.8 6.0 Unit pF pF pF pF RAS, CAS, WE, CS, CKE, DQM Address (x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15) 7 of 14 Rev. 1.1 May 2006 K4S280432I www.DataSheet4U.com K4S280832I K4S281632I DC CHARACTERISTICS (x4, x8) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current Symbol Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable CKE ≤ VIL(max), tCC = 10ns CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable IO = 0 mA Page burst tRC ≥ tRC(min) CKE ≤ 0.2V C L Test Condition Synchronous DRAM Version 75 90 2 2 20 Unit Note ICC1 ICC2P mA 1 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N ICC2NS ICC3P mA mA 10 5 5 30 25 110 200 2 800 mA mA mA mA mA mA uA 1 2 3 4 ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N ICC3NS ICC4 ICC5 ICC6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S2804(08)32I-T(U)C 4. K4S2804(08)32I-T(U)L 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ) 8 of 14 Rev.