1M x 32Bit x 4 Banks Mobile SDRAM

www.DataSheet4U.com K4M283233H - F(H)N/G/L/F 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES • 3.0V & 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) -. DS (Driver Strength) • DQM for masking. • Auto refresh. • • • • 64ms refresh period (4K cycle). Commercial Temperature Operation (-25°C ~ 70°C). Extended Temperature Operation (-25°C ~ 85°C). 90Balls FBGA ( -FXXX -Pb, -HXXX -Pb Free). Mobile SDRAM GENERAL DESCRIPTION The K4M283233H is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. K4M283233H-F(H)N/G/L/F60 K4M283233H-F(H)N/G/L/F75 K4M283233H-F(H)N/G/L/F7L Max Freq. 166MHz(CL=3) 133MHz(CL=3), 111MHz(CL=2) 133MHz(CL=3)*1, 83MHz(CL=2) LVCMOS 90 FBGA Pb (Pb Free) Interface Package - F(H)N/G : Low Power, Extended Temperature(-25°C ~ 85°C) - F(H)L/F : Low Power, Commercial Temperature(-25°C ~ 70°C) Notes : 1. In case of 40MHz Frequency, CL1 can be supported. Address configuration Organization 4M x 32 Bank BA0, BA1 Row A0 - A11 Column Address A0 - A7 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. 1 January 2006 K4M283233H - F(H)N/G/L/F FUNCTIONAL BLOCK DIAGRAM Mobile SDRAM I/O Control LWE Data Input Register Bank Select LDQM 1M x 32 Sense AMP 1M x 32 1M x 32 1M x 32 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register LRAS CLK CKE CLK ADD Column Decoder Col. Buffer LRAS LCBR Latency & Burst Length LCKE LCBR LWE LCAS Programming Register LWCBR LDQM Timing Register CS RAS CAS WE DQM 2 January 2006 K4M283233H - F(H)N/G/L/F Package Dimension and Pin Configuration < Bottom View*1 > E1 9 A B C D E F G D1 H J K L M N P R E Pin Name CLK CS A A1 b CKE A0 ~ A11 D e 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1 DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 2 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 Mobile SDRAM < Top View*2 > 90Ball(6x15) FBGA 3 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS 7 VDD VDDQ DQ22 DQ17 NC A2 A10 NC BA0 CAS VDD DQ6 DQ1 VDDQ VDD 8 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 CS WE DQ7 DQ5 DQ3 VSSQ DQ0 9 DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 A11 RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 Pin Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground [Unit:mm] z BA0 ~ BA1 RAS CAS WE DQM0 ~ DQM3 DQ0 ~ 31 < Top View*2 > #A1 Ball Origin Indicator SAMSUNG Week 3 K4M283233H-XXXX VDD/VSS VDDQ/VSSQ Symbol A A1 E E1 D D1 e b z Min 0.25 7.90 12.90 0.45 - Typ 8.00 6.40 13.00 11.20 0.80 0.50 - Max 1.00 8.10 13.10 0.55 0.10 January 2006 K4M283233H - F(H)N/G/L/F ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1.0 50 Mobile SDRAM Unit V V °C W mA NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C ~ 85°C for Extended, -25°C ~ 70°C for Commercial) Parameter Supply voltage VDDQ Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current VIH VIL VOH VOL ILI 2.7 2.2 -0.3 2.4 -2 3.0 3.0 0 3.6 VDDQ + 0.3 0.5 0.4 2 V V V V V uA 1 2 3 IOH = -2mA IOL = 2mA 4 Symbol VDD Min 2.7 Typ 3.0 Max 3.6 Unit V Note 1 NOTES : 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VIH (max) = 5.3V AC.The overshoot voltage duration is ≤ 3ns. 3. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 4. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 5. Dout is disabled, 0V ≤ VOUT ≤ VDDQ. CAPACITANCE (VDD = 3.0V & 3.3V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV) Pin Clock RAS, CAS, WE, CS, CKE, DQM Address DQ0 ~ DQ31 Symbol CCLK CIN CADD COUT Min 1.5 1.5 1.5 2.0 Max 3.5 3.0 3.0 4.5 Unit pF pF pF pF Note 4 January 2006 K4M283233H - F(H)N/G/L/F DC CHARACTERISTICS Mobile SDRAM Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial) Version Parameter Symbol Test Condition -60 Operating Current (One Bank Active) Precharge Standby Current in power-down mode Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≤ VIL(max), tCC = 10ns -75 -7L Unit Note ICC1 80 65 65 mA 1 ICC2P 0.5 mA 0.5 12 mA 5 5 mA 2 25 mA ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns Precharge Standby Current in non power-down mode CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ ICC2NS Input signals are stable ICC3P CKE ≤ VIL(max), tCC = 10ns Active Standby Current in power-down mode ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC ≥ tRC(min) -N/L Internal TCSR 45 *4 200 150 130 Active Standby Current in non power-down mode (One Bank Active) ICC3NS 15 mA Operating Current (Burst Mode) ICC4 100 75 65 mA 1 Refresh Current ICC5 140 130 330 120 mA uA 2 85/70 330 230 190 °C 3 Self Refresh Current ICC6 CKE ≤ 0.2V -G/F Full Array 1/2 of Full Array 1/4 of Full Array uA NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Internal TCSR can be supported. In comercial Temp : 45°C/Max 70°C. In extended Temp : 45°C/Max 85°C. 4. It has +/-5 °C tolerance. 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ). 5 January 2006 K4M283233H - F(H)N/G/L/F Mobile SDRAM AC OPERATING TEST CONDITIONS(VDD = 2.7V ∼ 3.6V, TA = -25 ~ 85°C for Extended, -25 ~ 70°C for Commercial) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4 / 0.4 0.5 x VDDQ tr/tf = 1/1 0.5 x VDDQ See Figure 2 Unit V V ns V VDDQ 1200Ω Output VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA 870Ω 30pF Output Z0=50Ω Vtt=0.5 x VDDQ 50Ω 30pF Figure 1. DC Output Load Circuit Figure 2. AC Output Load Circuit 6 January 2006 K4M283233H - F(H)N/G/L/F OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Version Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time tRAS(max) Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Number of valid output data Number of valid output data tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 CAS latency=1 60 100 63 2 tRDL + tRP 1 1 1 2 1 0 67.5 Symbol -60 tRRD(min) tRCD(min) tRP(min) tRAS(min) 12 18 18 42 -75 15 18 18 45 -7L 15 22.5 22.5 45 Mobile SDRAM Unit ns ns ns ns us ns CLK CLK CLK CLK Note 1 1 1 1 1 2 3 2 2 4 ea 5 NOTES: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP). 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. 6. Maximum burst refresh cycle : 8 7 January 2006 K4M283233H - F(H)N/G/L/F AC CHARACTERISTICS(AC operating conditions unless otherwise noted) - 60 Parameter CLK cycle time CLK cycle time CLK cycle time CLK to valid output delay CLK to valid output delay CLK to valid o