In-System Programmable

ispClock 5600 Family ™ In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer November 2004 Preliminary Data Sheet Features ■ ■ ■ ■ 10MHz to 320MHz Input/Output Operation Low Output to Output Skew (<50ps) Low Jitter Peak-to-Peak (<60ps) Up to 20 Programmable Fan-out Buffers • Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, SSTL, LVDS, LVPECL • Programmable output impedance - 40 to 70Ω in 5Ω increments • Programmable slew rate • Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V • Programmable lock detect • Multiply and divide ratio controlled by - Input divider (5 bits) - Feedback divider (5 bits) - Five output dividers (5 bits) • Programmable On-chip Loop Filter • Up to +/- 12ns skew range • Coarse and fine adjustment modes ■ Up to Five Clock Frequency Domains ■ Flexible Clock Reference and External Feedback Inputs • Programmable input standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL • Clock A/B selection multiplexer • Feedback A/B selection multiplexer • Programmable termination ■ Four User-programmable Profiles Stored in E2CMOS® Memory • Supports both test and multiple operating configurations ■ Fully Integrated High-Performance PLL www.DataSheet4U.com ■ Precision Programmable Phase Adjustment (Skew) Per Output • 16 settings; minimum step size 195ps - Locked to VCO frequency ■ Full JTAG Boundary Scan Test In-System Programming Support ■ Exceptional Power Supply Noise Immunity ■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges ■ 100-pin and 48-pin TQFP Packages ■ Applications • Circuit board common clock generation and distribution • PLL-based frequency generation • High fan-out clock buffer • Zero-delay clock buffer Product Family Block Diagram LOCK DETECT OUTPUT DIVIDERS BYPASS MUX * V0 V1 V2 V3 V4 PLL CORE Internal/External Feedback Select * OUTPUT ROUTING MATRIX CLOCK OUTPUTS SKEW CONTROL OUTPUT DRIVERS REFERENCE INPUTS M PHASE/ FREQUENCY DETECTOR FILTER VCO N FEEDBACK INPUTS JTAG INTERFACE & E2CMOS MEMORY Multiple Profile Management Logic 0 1 2 3 INTERNAL FEEDBACK PATH * Input Available only on ispClock5620 © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 clk5600_01 Lattice Semiconductor ispClock5600 Family Data Sheet General Description and Overview The ispClock5610 and ispClock5620 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications. The ispClock5610 provides up to 10 single-ended or five differential clock outputs, while the ispClock5620 provides up to 20 single-ended or 10 differential clock outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent programmable control of termination, slew-rate, and timing skew. All configuration information is stored on-chip in nonvolatile E2CMOS memory. The ispClock5600’s PLL and divider systems supports the synthesis of clock frequencies differing from that of the reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-dividers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feedback may be taken internally from the output of any of the five V-dividers, or externally through FBKA+/- or FBKB+/- pins. The core functions of all members of the ispClock5600 family are identical, the differences between devices being restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional block diagrams of the ispClock5610 and ispClock5620. Table 1. ispClock5600 Family Members Device ispClock5610 ispClock5620 Ref. Input Pairs 1 2 Feedback Input Pairs 1 2 Clock Outputs 10 20 Figure 1. ispClock5610 Functional Block Diagram PS0 PS1 LOCK RESET PLL_BYPASS SGATE GOE OEX OEY Profile Select Control OUTPUT ENABLE CONTROLS 0 1 2 3 LOCK DETECT OUTPUT DIVIDERS V0 (2-64) OUTPUT ROUTING MATRIX SKEW CONTROL OUTPUT DRIVERS BANK_0A BANK_0B BANK_2A BANK_2B BANK_4A BANK_4B BANK_5A BANK_5B BANK_7A BANK_7B INPUT DIVIDER REFA+ REFAREFVTT M (1-32) 1 V1 (2-64) PHASE DETECT LOOP FILTER V2 (2-64) VCO 0 V3 (2-64) N (1-32) FEEDBACK DIVIDER V4 (2-64) E 2 Configuration FBKA+ FBKA FBKVTT JTAG INTERFACE FEEDBACK SKEW ADJUST TDI TMS TCK TDO 2 Lattice Semiconductor Figure 2. ispClock5620 Functional Block Diagram PS0 PS1 LOCK RESET PLL_BYPASS SGATE GOE OEX ispClock5600 Family Data Sheet OEY SKEW CONTROL OUTPUT DRIVERS BANK_0A BANK_0B BANK_1A Profile Select Control OUTPUT ROUTING MATRIX OUTPUT ENABLE CONTROLS 0 1 2 3 LOCK DETECT BANK_1B BANK_2A BANK_2B OUTPUT DIVIDERS V0 BANK_3A BANK_3B BANK_4A REFSEL REFA+ REFA0 (2-64) INPUT DIVIDER M (1-32) 1 V1 (2-64) BANK_4B REFVTT 1 REFB+ REFB- PHASE DETECT LOOP FILTER V2 (2-64) VCO 0 V3 (2-64) SKEW CONTROL OUTPUT DRIVERS BANK_5A BANK_5B N (1-32) FEEDBACK DIVIDER V4 (2-64) FBKSEL FBKA+ FBKA0 BANK_6A BANK_6B E 2 Configuration BANK_7A BANK_7B BANK_8A BANK_8B BANK_9A JTAG INTERFACE FEEDBACK SKEW ADJUST BANK_9B FBKVTT 1 FBKB+ FBKB- TDI TMS TCK TDO 3 Lattice Semiconductor ispClock5600 Family Data Sheet Absolute Maximum Ratings ispClock5600V Core Supply Voltage VCCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V PLL Supply Voltage VCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V JTAG Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V Output Driver Supply Voltage VCCO . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V Output Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130°C 1. When applied to an output when in high-Z condition Recommended Operating Conditions ispClock5600V Symbol VCCD VCCJ VCCA VCCXSLEW TJOP TA Parameter Core Supply Voltage JTAG I/O Supply Voltage Analog Supply Voltage VCC Turn-on Ramp Rate Operating Junction Temperature Ambient Operating Temperature All supply pins Commercial Industrial Commercial Industrial Conditions Min. 3.0 1.62 3.0 — 0 -40 0 -40 Max. 3.6 3.6 3.6 0.33 100 115 701 851 Units V V V V/µs °C °C 1. Device power dissipation may also limit maximum ambient operating temperature. Recommended Operating Conditions – VCCO vs. Logic Standard VCCO (V) Logic Standard LVTTL LVCMOS 1.8V LVCMOS 2.5V LVCMOS 3.3V SSTL2 Class 1 SSTL3 Class 1 HSTL Class 1 LVPECL (Differential) LVDS VCCO = 2.5V VCCO = 3.3V Min. 3.0 1.71 2.375 3.0 2.375 3.0 1.425 3.0V 2.375 3.0 Typ. 3.3 1.8 2.5 3.3 2.5 3.3 1.5 3.3V 2.5V 3.3 Max. 3.6 1.89 2.625 3.6 2.625 3.6 1.575 3.6V 2.625 3.6 Min. — — — — 1.15 1.30 0.68 — — — VREF (V) Typ. — — — — 1.25 1.50 0.75 — — — Max. — — — — 1.35 1.70 0.90 — — — Min. — — — — VREF - 0.04 VREF - 0.05 — — — — VTT (V) Typ. — — — — — VREF 0.5 x VCCO — — — Max. — — — — VREF + 0.04 VREF + 0.05 — — — — Note: ‘—’ denotes VREF or VTT not applicable to this logic standard E2CMOS Memory Write/Erase Characteristics Parameter Erase/Reprogram Cycles Conditions Min. 1000 Typ. — Max. — Units 4 Lattice Semiconductor ispClock5600 Family Data Sheet Performance Characteristics – Power Supply Symbol ICCD ICCA ICCO Parameter Core Supply Current Analog Supply Current Output Driver Supply Current (per Bank) Conditions fVCO = 640MHz fVCO = 640MHz VCCO = 1.8V , LVCMOS VCCO = 2.5V1, LVCMOS VCCO = 3.3V1, LVCMOS VCCO = 3.3V2, LVDS VCCJ = 1.8V VCCJ = 2.5V VCCJ = 3.3V 1 Typ. 150 5.5 13 18 24 7.5 200 300 300 Max. 160 7 15 24 35 8 300 400 400 Units mA mA mA ICCJ JTAG I/O Supply Current (static) µA 1. Supply current consumed by each bank, both outputs active, 18pF load, 320MHz output frequency. 2. Supply current consumed by each bank, 100Ω, 5pf differential load, 320MHz output frequency. DC Electrical Characteristics – Single-ended Logic VIL (V) Logic Standard LVTTL/LVCMOS 3.3V LVCMOS 1.8V LVCMOS 2.5V SSTL2 Class 1 SSTL3 Class 1 HSTL Class 1 Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max. 0.8 0.35VCCO 0.7 VREF - 0.2 VREF - 0.1 Min. 2 0.65VCCO 1.7 VREF + 0.2 VREF + 0.1 VIH (V) Max. 3.6 3.6 3.6 3.6 3.6 3.6 VOL Max. (V) VOH Min. (V) 0.4 0.4 0.4 0.54 0.9 2 2 IOL (mA) 4 1 1 IOH (mA) -41 -41 -41 -7.6 -8 -8 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.81 VCCO - 1.3 2 2 4 41 7.6 8 8 VREF - 0.18 VREF + 0.18 0.43 VCCO - 0.43 1. Specified for 50Ω internal series output termination. 2. Specified for 40Ω internal series output termination. 3. Specified for ≈20Ω internal series output termination. DC Electrical Characteristics – LVDS Symbol VICM VTHD VIN VOH VOL VOD ∆VOD VOS ∆VOS ISA ISAB Parameter Common Mode Input Voltage Differential Input Threshold Input Voltage Output High Voltage Output Low Voltage Output Voltage Differential Change in VOD between H and L Output Voltage Offset Change in VOS Between H and L Output Short Circuit Current Output Short Circuit Current VOD = 0V, Outputs Shorted to GND VOD = 0V, Outputs Shorted to Each Other Common Mode Output Voltage RT = 100Ω RT = 100Ω RT = 100Ω Conditions Min. 0