600mA Low Quiescent Current 1.6MHz High Efficiency Synchronous Buck Regulator

® ISL9105 Data Sheet February 13, 2007 FN6415.1 600mA Low Quiescent Current 1.6MHz High Efficiency Synchronous Buck Regulator ISL9105 is a 600mA, 1.6MHz step-down regulator that is ideal for powering low-voltage microprocessors in handheld devices such as PDAs and cellular phones. It is optimized for generating low output voltages down to 0.8V. The supply voltage range is from 2.7V to 5.5V allowing the use of a single Li+ cell, three NiMH cells or a regulated 5V input. It has a guaranteed minimum output current of 600mA. 1.6MHz pulse-width modulation (PWM) switching frequency allows using small external components. It has flexible operation mode selection of forced PWM mode and low IQ mode with typical 25μA quiescent current for highest light load efficiency to maximize battery life. The ISL9105 includes a pair of low on-resistance P-Channel and N-Channel internal MOSFETs to maximize efficiency and minimize external component count. 100% duty-cycle operation allows less than 200mV dropout voltage at 600mA output current. The ISL9105 offers a typical 216ms Power-On-Reset (POR) timer at power-up. The timer output can be reset by RSI. When shutdown, ISL9105 discharges the output capacitor. Other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. The ISL9105 is offered in a 2mmx3mm 8 Ld DFN package with 1mm maximum height. The complete converter occupies less than 1cm2 area. Features • High Efficiency Synchronous Buck Regulator with up to 95% Efficiency • Selectable Forced PWM Mode and SKIP Mode • 25μA Quiescent Supply Current in SKIP Mode • 2.7V to 5.5V Supply Voltage • 216ms POR Timer • 3% Output Accuracy Over Temperature/Line/Load • 600mA Guaranteed Output Current • Less Than 1μA Logic Controlled Shutdown Current • 100% Maximum Duty Cycle for Lowest Dropout • Discharge Output Capacitor when Shutdown • Internal Loop Compensation • Internal Digital Soft-Start • Peak Current Limit Protection, Short Circuit Protection • Over-Temperature Protection • Enable • Small 8 Ld 2x3mm DFN • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Single Li-Ion Battery-Powered Equipment • DSP Core Power Ordering Information(to be updated) PART NUMBER (NOTE) ISL9105IRZ-T TEMP. RANGE PART (°C) MARKING 05Z PACKAGE (Pb-free) PKG. DWG. # • PDAs and Palmtops Pinout ISL9105 (8 LD DFN) TOP VIEW -40 to +85 8 Ld 2x3 DFN L8.2x3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. VIN EN POR MODE 1 2 3 4 8 7 6 5 PHASE GND FB RSI 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL9105 Absolute Maximum Ratings (Reference to GND) Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V EN, RSI, MODE, POR . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V Thermal Information Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) 2x3 DFN Package . . . . . . . . . . . . . . 75 6 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 600mA Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specification are measured at the following conditions: TA = +25°C, VIN = 3.6V, EN = VIN, RSI = MODE = 0V, L = 3.3μH, C1 = 10μF, C2 = 10μF, IOUT = 0A (see the Typical Application Circuit). SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PARAMETER SUPPLY VIN Under Voltage Lockout Threshold VUVLO Rising Falling 2.2 - 2.5 2.4 25 5 0.1 2.7 50 8 2 V V μA mA μA Quiescent Supply Current IVIN MODE = VIN, no load at the output MODE = GND, no load at the output Shutdown Supply Current OUTPUT REGULATION FB Regulation Voltage ISD VIN = 5.5V, EN = low VFB TA = 0°C to +85°C TA = -40°C to +85°C 0.784 0.78 -3 600 0.8 0.8 0.1 0.2 - 0.816 0.82 3 - V V μA % %/V mA FB Bias Current Output Voltage Accuracy Line Regulation Maximum Output Current COMPENSATION Error Amplifier Trans-Conductance PHASE P-Channel MOSFET On Resistance N-Channel MOSFET On Resistance P-Channel MOSFET Peak Current Limit PHASE Maximum Duty Cycle PWM Switching Frequency PHASE Minimum On Time Soft-Start-Up Time POR Output Low Voltage Delay Time POR Pin Leakage Current IFB FB = 0.75V VIN = VO + 0.5V to 5.5V, IO = 0mA to 600mA VIN = VO + 0.5V to 5.5V (minimal 2.7V) Design info only - 20 - μA/V VIN = 3.6V, IO = 200mA VIN = 3.6V, IO = 200mA IPK 0.75 - 0.16 0.14 1.0 100 1.6 1.1 0.22 0.22 1.3 1.8 140 - Ω Ω A % MHz ns ms fS MODE = low (forced PWM mode) 1.2 - Sinking 1mA, FB = 0.7V 150 216 0.01 0.3 275 0.1 V ms μA POR = VIN = 3.6V - 2 FN6415.1 February 13, 2007 ISL9105 Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specification are measured at the following conditions: TA = +25°C, VIN = 3.6V, EN = VIN, RSI = MODE = 0V, L = 3.3μH, C1 = 10μF, C2 = 10μF, IOUT = 0A (see the Typical Application Circuit). (Continued) SYMBOL TEST CONDITIONS MIN 1.2 Percentage of nominal regulation voltage Percentage of nominal regulation voltage Percentage of nominal regulation voltage Percentage of nominal regulation voltage 89.5 85 105.5 102 TYP 92 88 108 105 64 MAX 94.5 91 110.5 108 UNITS V % % % % μs PARAMETER Minimum Supply Voltage for Valid POR Signal Internal PGOOD Low Rising Threshold Internal PGOOD Low Falling Threshold Internal PGOOD High Rising Threshold Internal PGOOD High Falling Threshold Internal PGOOD Delay Time EN, MODE, RSI Logic Input Low Logic Input High Logic Input Leakage Current Thermal Shutdown Thermal Shutdown Hysteresis 1.4 Pulled up to 5.5V - 0.1 150 25 0.4 1 - V V μA °C °C Pin Descriptions VIN Input supply voltage. Connect a 10μF ceramic capacitor to power ground. PHASE Switching node connection. Connect to one terminal of inductor. GND System ground. EN Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output capacitor when driven to low. Do not leave this pin floating. FB Buck regulator output feedback. Connect to the output through a voltage divider resistor. POR 216ms timer output. At power-up or EN HI, this output is a 216ms delayed Power-Good signal for the output voltage. This output can be reset by a low RSI signal. 216ms starts when RSI goes to high. RSI This input resets the 216ms timer. When the output voltage is within the PGOOD window, an internal timer is started and generates a POR signal 216ms later when RSI is low. A high RSI resets POR and RSI high to low transition restarts the internal counter if the output voltage is within the window, otherwise the counter is reset by the output voltage condition. MODE Mode Selection pin. Connect to logic high or input voltage VIN for low IQ mode; connect to logic low or ground for forced PWM mode. Do not leave this pin floating. Exposed Pad The exposed pad must be connected to the GND pin for proper electrical performance. The exposed pad must also be connected to as much as possible for optimal thermal performance. 3 FN6415.1 February 13, 2007 ISL9105 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 3.6V, EN = VIN, RSI = MODE = 0V, L = 3.3µH, C1 = 10µF, C2 = 10µF, IOUT = 0A) 100 VO = 2.5V 90 EFFICIENCY (%) EFFICIENCY (%) 90 VIN = 2.7V VIN = 3.6V 70 100 80 VO = 1.6V VO = 0.8V 80 70 60 60 VIN = 5.5V 50 1 10 100 LOAD CURRENT (mA) 1000 50 1 10 100 LOAD CURRENT (mA) 1000 FIGURE 1. EFFICIENCY vs LOAD CURRENT (VIN = 3.6V) FIGURE 2. EFFICIENCY vs LOAD CURRENT (VO = 1.6V) 1.640 I_LOAD = 0A 1.635 1.630 VOUT (V) 1.625 1.620 1.615 1.610 2.7 I_LOAD = 300mA I_LOAD = 600mA VOUT (V) 1.635 1.630 1.625 1.620 VIN = 3.6V 1.615 1.610 1.605 3.7 VIN (V) 4.7 0 100 200 300 400 OUTPUT CURRENT (mA) 500 600 VIN = 2.7V VIN = 5.5V FIGURE 3. LINE REGULATION FIGURE 4. LOAD REGULATION 40 35 INPUT CURRENT (mA) INPUT CURRENT (μA) 30 25 20 15 10 5 0 2.73 0.20 3.74 VIN (V) 0.20 4.70 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.7 3.2 3.7 VIN (V) 4.2 4.7 FIGURE 5. I_Q vs VIN (PFM) FIGURE 6. I_Q vs VIN (PWM) 4 FN6415.1 February 13, 2007