®
ISL8723, ISL8724
Data Sheet December 21, 2006 FN6413.0
Power Sequencing Controllers
The Intersil ISL8723 and ISL8724 are 4 channel sequencers controlling the on and off sequence of voltages with under voltage supply fault protection and a “sequence completed” signal (RESET#). For larger systems, more than 4 voltages can be sequenced by a simple connection of multiple IC's. These sequencers use an integrated charge pump to drive 4 external low-cost N-channel MOSFET switch gates above the IC bias voltage by 5.3V. These IC's can be biased from and control any supply from 2.5V to 5V and additionally monitor any voltage above 0.7V. Individual product descriptions are below. The four channel ISL8723 (ENABLE input), ISL8724 (ENABLE# input) offer the designer 4 voltage control when it is required that all four rails are in minimal compliance prior to turn on and that compliance must be maintained during operation. The ISL8723 has a low power standby mode when it is disabled suitable for battery powered applications. External resistors provide flexible voltage threshold programming of monitored voltages. Delay and sequencing timing are programmable by external capacitors for both ramp up and ramp down.
Features
• Enables arbitrary turn-on and turn-off sequencing of up to four power supplies (0.7V to 5V) • Operates from 2.5V to 5V supply voltage • Supplies VDD +5.3V of charge pumped gate drive • Adjustable voltage slew rate for each rail • Multiple sequencers can be easily daisy-chained to sequence an infinite number of independent voltages • Glitch immunity • Under voltage lockout for each monitored supply voltage • 30µA Sleep State (ISL8723) • Active high (ISL8723) or low (ISL8724) ENABLE# input • Pb-free plus anneal available (RoHS compliant) QFN Package
Applications
• Graphics cards • FPGA/ASIC/microprocessor/PowerPC supply sequencing • Network Routers • Telecommunications Systems
Ordering Information
PART NUMBER ISL8723IRZ (Note) ISL8724IRZ (Note) TEMP. RANGE PART (°C) MARKING 8723IRZ 8724IRZ PACKAGE PKG. DWG. #
Pinout
ISL8723, ISL8724 (24 LD QFN) TOP VIEW
DLY_ON_A SYSRST# UVLO_A 20 RESET#
-40 to +85 24 Ld 4x4 QFN L24.4x4 (Pb-free) L24.4x4 -40 to +85 24 Ld 4x4 QFN L24.4x4 (Pb-free) L24.4x4 Tape & Reel
ENABLE/ ENABLE# GATE_A DLY_OFF_C DLY_OFF_D GATE_B GATE_C 1 2 3
VDD
ISL8723IRZ-T (Note) 8723IRZ ISL8724IRZ-T (Note) 8724IRZ ISL8723EVAL1
24
23
22
21
19 18 DLY_OFF_A 17 UVLO_C 16 DLY_ON_C
Evaluation Platform
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4mmx4mm 4 5 6 7 GATE_D 8 DLY_ON_B 9 NC 10 GND 11 NC 12 UVLO_B 15 DLY_ON_D 14 UVLO_D 13 DLY_OFF_B
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
NC
ISL8723, ISL8724
AIN BIN CIN DIN AOUT BOUT COUT DOUT
GATE D
GATE C
GATE B
GATE A
DIN
CIN
BIN
VDD ENABLE SYSRST# RESET# DLY_OFF_B GROUND DLY_OFF_A DLY_ON_A DLY_ON_B DLY_ON_C
UVLO_A UVLO_B UVLO_C UVLO_D DLY_OFF_C DLY_OFF_D DLY_ON_D
FIGURE 1. TYPICAL ISL8723 APPLICATION USAGE
Pin Descriptions
PIN # 23 10 1 24 PIN NAME VDD GND ENABLE/ ENABLE# RESET# FUNCTION Chip Bias Bias Return Input to start on/off sequencing. RESET# Output Bias IC from nominal 2.5V to 5V IC ground Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is disabled for 10ms after UVLO is satisfied. ISL8723 has ENABLE. ISL8724 has ENABLE#. RESET# provides a high signal ~160ms after all GATEs are fully enhanced. This delay is for stabilization of output voltages. RESET# will assert low upon any UVLO not being satisfied or ENABLE/ENABLE# being deasserted. The RESET# output is an open drain N-channel FET and is guaranteed to be in the correct state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X. These inputs provide for a programmable UV lockout referenced to an internal 0.631V reference and are filtered to ignore short (<7µs) transients below programmed UVLO level. DESCRIPTION
20 12 17 14 21 8 16 15 18 13 3 4 2 5 6 7
UVLO_A UVLO_B UVLO_C UVLO_D DLY_ON_A DLY_ON_B DLY_ON_C DLY_ON_D
Under Voltage Lock Out/Monitoring Input
Gate On Delay Timer Output
Allows for programming the delay and sequence for VOUT turn-on using a capacitor to ground. Each cap is charged with 1µA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current source providing delayed enhancement of the associated FETs GATE to turn-on.
DLY_OFF_A Gate Off Delay Timer Output DLY_OFF_B DLY_OFF_C DLY_OFF_D GATE_A GATE_B GATE_C GATE_D FET Gate Drive Output
Allows for programming the delay and sequence for VOUT turn-off through ENABLE/ENABLE# via a capacitor to ground. Each cap is charged with a 1µA internal current source to an internal reference voltage causing the corresponding gate to be pulled down thus turning-off the FET.
Drives the external FETs with a 10µA current source to soft start ramp into the load. During sequence off, 10µA is sunk from this pin to control the FET turn-off. During a turn-off due to a fault, the gate will sink ~75mA to ensure a rapid turn-off.
2
AIN
FN6413.0 December 21, 2006
ISL8723, ISL8724 Pin Descriptions
PIN # 22 PIN NAME SYSRST# (Continued)
FUNCTION System Reset I/O
DESCRIPTION As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low. This pin can also be used to initiate the programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from input signal on this pin being driven high to first GATE. As an output when there is a UV condition this pin pulls low. If common to other SYSRST# pins in a multiple IC configuration it will cause immediate and unconditional latch-off of all other GATEs on all other ISL872x sequencers. This pin is released to go high once all UVLO and enable conditions are satisfied and is pulled low concurrent with the last GATE being turned off after EN disabled.
9,11, 19
No Connect
No Connect
No Connect
3
FN6413.0 December 21, 2006
ISL8723, ISL8724
Absolute Maximum Ratings
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V UVLO, ENABLE, ENABLE#, SYSRST# . . . . . . -0.3V to VDD +0.3V RESET#, DLY_ON, DLYOFF . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) 4 x 4 QFN Package . . . . . . . . . . . . . . . 48 9 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +125°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +2.5V to +5.0V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 3. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER UVLO
VDD = 3.3V to +5V, TA = TJ = -40°C to +85°C, Unless Otherwise Specified. SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Undervoltage Lockout Falling Threshold Undervoltage Lockout Falling Threshold Undervoltage Lockout Hysteresis Undervoltage Lockout Threshold Range Undervoltage Lockout Delay Transient Filter Duration DELAY ON/OFF Delay Charging Current Delay Charging Current Range Delay Threshold Voltage
VUVLOvth VUVLOvth VUVLOhys RUVLOvth TUVLOdel tFIL
TA = TJ = +25°C
619 604 -
631 631 9 6 10 7
647 656 18 -
mV mV mV mV ms μs
Max VUVLOvth- Min VUVLOvth ENABLE satisfied VDD, UVLO, ENABLE glitch filter
-
DLY_ichg DLY_ichg_r DLY_Vth
VDLY = 0V DLY_ichg(max) - DLY_ichg(min)
0.9 1.21
1 0.01 1.273
1.115 0.05 1.32
μA μA V
ENABLE/ENABLE#, RESET# AND SYSRST# I/O ENABLE Threshold ENABLE# Threshold ENABLE/ENABLE# Hysteresis ENABLE/ENABLE# Lockout Delay ENABLE/ENABLE# Input Capacitance RESET# Pull-up Voltage RESET# Pull-Down Current RESET# Delay after GATE High RESET# Output Low RESET Output Capacitance SYSRST# Pull-up Voltage SYSRST# Pull-up Current SYSRST# Pull Down Current SYSRST# Low Output Voltage VENh VENh VENh -VENl TdelEN_LO Cin_en Vpu_rst IRSTpd5 TRSTdel VRSTl Cout_rst Vpu_srst Ipu_srst Ipu_5 Vol_srst VDD = 3.3V, SYSRST# = 0.5V VDD = 5V VDD = 5V, IOUT = 100μA VDD = 5V, RST = 0.1V GATE = VDD+5V Measured at VDD = 5V, 1mA sourcing current Measured at VDD = 5V UVLO satisfied, EN to DLY_ON Measured at VDD = 5V 1.28 0.5 VDD 0.1 10 5 VDD 13 160 10 VDD-0.5V 12 2.7 1.35 0.2 0.1 0.1 V V V ms pF V mA ms V pF V μA μA V
4
FN6413.0 December 21, 2006
ISL8723, ISL8724
Electrical Specifications
PARAMETER SYSRST# Output Capacitance SYSRST# Low to GATE Turn-off SYSRST# High to GATE Turn-on GATE GATE Turn-On Current GATE Turn-Off Current GATE Current Range GATE Pull-Down High Current GATE High Voltage GATE Low Voltage BIAS IC Supply Current I
