Description
® ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A Data Sheet October 12, 2006 FN6381.0 Adjustable Quad Sequencer The ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A family of ICs provide four delay adjustable sequenced outputs while monitoring an input voltage all with a minimum of external components. High performance DSP, FPGA, µP and various sub-systems require input power sequencing for proper functionality at initial power up and the ISL870XA provides this function while monitoring the distributed voltage for over and undervoltage compliance. These ICs operate over the +3.3V to +24V nominal voltage range. All have a user adjustable time from UV and OV voltage compliance to sequencing start via an external capacitor when in auto start mode and adjustable time delay to subsequent ENABLE output signal via external resistors. Additionally, the ISL8702A, ISL8703A, ISL8704A and ISL8705A provide I/O for sequencing on and off operation (SEQ_EN) and for voltage window compliance reporting (FAULT) over the +3.3V to +24V nominal voltage range. Easily daisy chained for more than 4 sequenced signals. Altogether, the ISL870XA provides these adjustable features with a minimum of external BOM. See Figure 1 for typical implementation. Features • Adjustable Delay to Subsequent Enable Signal • Adjustable Delay to Sequence Auto Start • Adjustable Distributed Voltage Monitoring • Under and Overvoltage Adjustable Delay to Auto Start Sequence • I/O Options ENABLE (ISL8700A, ISL8702A, ISL8704A) and ENABLE# (ISL8701A, ISL8703A, ISL8705A) SEQ_EN (ISL8702A, ISL8703A) and SEQ_EN# (ISL8704A, ISL8705A) • Voltage Compliance Fault Output • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Power Supply Sequencing • System Timing Function Pinout ISL870XA (14 LD SOIC) TOP VIEW ENABLE_D 1 14 VIN 13 TD 12 TC 11 TB 10 TIME 9 SEQ_EN (NC on ISL8700A/01A) 8 FAULT (NC on ISL8700A/01A) Ordering Information PART NUMBER (Note 1) ISL8700AIBZ* ISL8701AIBZ* ISL8702AIBZ* ISL8703AIBZ* ISL8704AIBZ* ISL8705AIBZ* PART MARKING ISL8700AIBZ ISL8701AIBZ ISL8702AIBZ ISL8703AIBZ ISL8704AIBZ ISL8705AIBZ TEMP. RANGE (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-free) 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC PKG. DWG. # M14.15 M14.15 M14.15 M14.15 M14.15 M14.15 3.3-24V ENABLE_C 2 ENABLE_B 3 ENABLE_A 4 OV 5 UV 6 GND 7 ISL8701A, ISL8703A, ISL8705A PINS 1-4 ARE ENABLE# FUNCTION ISL8704A, ISL8705A PIN 9 IS SEQ_EN# FUNCTION ISL870XAEVAL1 Evaluation Platform *Add “-T” suffix for tape and reel. NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Ru UV Rm OV VIN SEQ_EN * EN DC/DC ENABLE_A ENABLE_B ENABLE_C ENABLE_D FAULT * Vo1 EN DC/DC Vo2 GND TB TC TD TIME Rl EN DC/DC Vo3 EN DC/DC V04 * SEQ_EN and FAULT are not available on ISL8700A and ISL8701A FIGURE 1. ISL870XA IMPLEMENTATION 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A Absolute Maximum Ratings VIN, ENABLE(#), FAULT . . . . . . . . . . . . . . . . . . . . . . . 27V, to -0.3V TIME, TB, TC, TD, UV, OV . . . . . . . . . . . . . . . . . . . . . +6V, to -0.3V SEQ_EN(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN+0.3V, to -0.3V ENABLE, ENABLE # Output Current . . . . . . . . . . . . . . . . . . . 10mA Thermal Information Thermal Resistance (Typical, Note 2) θJA (°C/W) 14 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C (SOIC Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage Range (Nominal). . . . . . . . . . . . . . . . . . 3.3V to 24V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER UV AND OV INPUTS UV/OV Rising Threshold UV/OV Falling Threshold UV/OV Hysteresis UV/OV Input Current Nominal VIN = 3.3V to +24V, TA = TJ = -40°C to+85°C, Unless Otherwise Specified. SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VUVRvth VUVFvth VUVhys IUV VUVRvth - VUVFvth 1.16 1.06 - 1.21 1.10 104 10 1.28 1.18 - V V mV nA TIME, ENABLE/ENABLE# OUTPUTS TIME Pin Charging Current TIME Pin Threshold Time from VIN Valid to ENABLE_A ITIME VTIME_VTH tVINSEQpd tVINSEQpd_10 tVINSEQpd500 Time from VIN Invalid to Shutdown ENABLE Output Resistance ENABLE Output Low ENABLE Pull-down Current Delay to Subsequent ENABLE Turn-on/off tshutdown REN Vol Ipulld tdel_120 tdel_3 tdel_0 SEQUENCE ENABLE AND FAULT I/O VIN Valid to FAULT Low VIN Invalid to FAULT High FAULT Pull-down Current SEQ_EN Pull-up Voltage SEQ_EN Low Threshold Voltage SEQ_EN High Threshold Voltage Delay to ENABLE_A Deasserted BIAS IC Supply Current IVIN_3.3V IVIN_12V IVIN_24V VIN Power On Reset VIN_POR VIN = 3.3V VIN = 12V VIN = 24V VIN low to high 191 246 286 2.3 400 2.8 μA μA μA V VSEQ VilSEQ_EN VihSEQ_EN tSEQ_EN_ENA SEQ_EN low to ENABLE_A low tFLTL tFLTH FAULT = 1V SEQ_EN open 15 10 1.2 30 0.5 15 2.4 0.2 50 0.3 1 μs μs mA V V V μs SEQ_EN = high, CTIME = open SEQ_EN = high, CTIME = 10nF SEQ_EN = high, CTIME = 500nF UV or OV to simultaneous shutdown IENABLE = 1mA IENABLE = 1mA ENABLE = 1V RTX = 120kΩ RTX = 3kΩ RTX = 0Ω 1.9 10 155 3.5 2.6 2.0 30 7.7 435 100 0.1 15 195 4.7 0.5 2.25 1 240 6 μA V μs ms ms μs Ω V mA ms ms ms 2 FN6381.0 October 12, 2006 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A Pin Descriptions PINS 8700A 8701A 8702A 8703A 8704A 8705A PIN NAME NA 1 NA 2 NA 3 NA 4 1 NA 2 NA 3 NA 4 NA NA 1 NA 2 NA 3 NA 4 1 NA 2 NA 3 NA 4 NA NA 1 NA 2 NA 3 NA 4 1 NA 2 NA 3 NA 4 NA FUNCTION DESCRIPTION ENABLE#_D Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output to sequence off for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias. ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output to sequence off for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V. ENABLE#_C Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced off after ENABLE#_D for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias. ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced off after ENABLE_D for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V. ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced off after ENABLE#_C for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias. ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced off after ENABLE_C for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V. ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced off after ENABLE#_B for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias. ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and sequenced off after ENABLE_B for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V. OV The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled high via external pull-ups. The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled high via external pull-ups. IC ground. The VIN voltage when not within the desired UV to OV window will cause FAULT to be released to be pulled high to a voltage equal to or less than VIN via an external resistor. This pin provides a sequence on signal input with a high input. Internally pulled high to ~2.4V. This pin provides a sequence on signal input with a low input. Internally pulled high to ~2.4V. This pin provides a 2.6µA current output so that an adjustable VIN valid to sequencing on and off start delay period is created with a capacitor to ground. A resistor connected from this pin to ground determines the time delay from ENABLE_A being active to ENABLE _B being active on turn-on and also going inactive on turn-off via the SEQ_IN input. A resistor connected from this pin to ground determines the time delay from ENABLE_B being active to ENABLE _C being active on turn-on and also going inactive on turn-off via the SEQ_IN input. A resistor connected from this pin to ground determines the time delay from ENABLE_C being active to ENABLE _D being active on turn-on and also going inactive on turn-off via the SEQ_IN input. IC Bias Pin Nominally 3.3V to 24V This pin requires a 1μF decoupling capacitor close to IC pin. 5 5 5 5 5 5 6 6 6 6 6 6 UV 7 NA NA NA 10 11 7 NA NA NA 10 11 7 8 9 NA 10 11 7 8 9

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ISL8705A

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