Two-Phase Buck PWM Controller

® ISL8121 Data Sheet October 18, 2006 FN6352.1 3V to 20V, Two-Phase Buck PWM Controller with Integrated 4A MOSFET Drivers The ISL8121 is a two-phase buck PWM controller featuring an input voltage range of 3V to 20V and integrated MOSFET drivers. Precision voltage regulation is provided for point-of-load and other high-current applications that require efficient and compact implementation. Multiphase buck converter architecture uses interleaved timing to multiply channel ripple frequency allowing smaller filter inductors and reducing input and output ripple currents due to the ripple cancellation effect. Lower ripple results in fewer input and output capacitors. Smaller and low cost transistors can be used resulting from the higher efficiency and reduced power dissipation. The ISL8121 offers an internal 0.6V reference with a system regulation accuracy of ±0.8% (Industrial Temperature range), an optional external reference input, and user-adjustable switching frequency. Unity gain differential amplifier targeted at remote voltage sensing capability enhances the regulation. A power good signal (PGD) is issued when the output voltage is within the regulated window. An internal shunt regulator with optional external connection capability extends the operational input voltage range. For applications requiring voltage tracking or sequencing, the ISL8121 offers a host of possibilities, including coincidental, ratiometric, or offset tracking, as well as sequential start-ups, user adjustable for a wide range of applications. Additional features include overvoltage and overcurrent protection. Overcurrent protection can be tailored to various applications with no need for additional parts. The ISL8121 uses cost and space-saving rDS(ON) sensing for channel current balance, dynamic voltage positioning, and overcurrent protection. Channel current balancing is automatic and accurate with the integrated current-balance control system. Features • Integrated Two-Phase Power Conversion • Precision Output Voltage Regulation - ±0.8% System Accuracy Over Temperature (Industrial) - Differential Remote Voltage Sensing for Increased Voltage Sensing Accuracy • Shunt Regulator for Wide Input Power Conversion - 5V and Higher Bias - Up to 20V Power Down-Conversion • Precision Channel Current Sharing - Loss-Less rDS(ON) Current Sampling • Integrated High Capable 4A Drivers • 0.6V Internal Reference • Full Spectrum Voltage Tracking - Coincidental, Ratiometric, or Offset • Sequential Start-up Control • Selectable Switching Frequency up to 2MHz Per Phase • Fast Transient Recovery Time • Overcurrent Protection • Overvoltage Protection • Capable of Start-up in a Pre-Biased Load • QFN Packages: - QFN - Compliant to JEDEC PUB95 MO-220 - QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • General Purpose High Current DC/DC Converters • High Current, Low Voltage FPGA/ASIC DC/DC Converters • Telecom System 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8121 Ordering Information PART NUMBER (Note) ISL8121IRZ ISL8121IRZ-T PART MARKING 8121IRZ 8121IRZ TEMP. (°C) PACKAGE (Pb-Free) PKG. DWG. # Pinout ISL8121 (QFN) TOP VIEW REFTRK BOOT1 20 PGD SS -40 to 85 24 Ld 4x4 QFN L24.4x4C VSENVSEN+ VMON VDIFF FB COMP 1 2 3 4 5 6 24 23 FS -40 to 85 24 Ld 4x4 QFN L24.4x4C 22 21 19 18 PHASE1 17 ISEN1 ISL8121EVAL1 Evaluation Platform NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. UG1 16 LG1 15 PVCC 14 LG2 13 ISEN2 12 PHASE2 25 GND 7 VREG 8 VCC 9 EN 10 BOOT2 11 UG2 2 FN6352.1 October 18, 2006 Block Diagram PGD FS EN VCC PVCC BOOT1 VMON 300mV + 110% 90% OSCILLATOR VCC 10µA 10µA 20µA 3 POWER-ON RESET (POR) GATE CONTROL PHASE1 UG1 OVP COMP 120% PWM1 LG1 ISL8121 ISL8121 REFTRK REFERENCE EA SOFT-START AND FAULT LOGIC GND CONTROL LOGIC BOOT2 FB + VDIFF VSENX1 PWM2 OC - Σ Σ VCC UG2 20µA VSEN+ CURRENT CORRECTION 20µA/1mA SHUNT LINEAR REGULATOR GATE CONTROL PHASE2 VREG VCC LG2 FN6352.1 October 18, 2006 ISEN1 ISEN2 SS ISL8121 Simplified Power System Diagram VIN Q1 EN PGD CHANNEL1 Q2 VOUT Q3 CHANNEL2 ISL8121 Q4 Typical Application VIN LIN RSHUNT CHFIN1 CF2 VCC VREG PVCC BOOT1 REFTRK UG1 FS RFS SS CSS VMON RPG PGD R4 EN UG2 R5 PHASE2 ISEN2 C1 COMP LG2 R2 C2 FB VDIFF R1 VSEN+ VSENGND Q4 RP LG1 BOOT2 ISEN1 RISEN1 Q2 PHASE1 Q1 LOUT1 CBOOT1 CBIN1 CF1 VOUT CBOOT2 CHFIN2 Q3 CBIN2 CHFOUT CBOUT ISL8121 RISEN2 LOUT2 RS 4 FN6352.1 October 18, 2006 ISL8121 Absolute Maximum Ratings Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Shunt Regulator Voltage, VVREG . . . . . . . . . . . . . . . -0.3V to +6.5V Boot Voltage, VBOOT . . . . . . . . . . . . . PGND - 0.3V to PGND + 27V Phase Voltage, VPHASE . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V Upper Gate Voltage, VUG . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V Lower Gate Voltage, VLG . . . . . . . . . . . PGND - 0.3V to VCC + 0.3V Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V Thermal Information Thermal Resistance θJA (°C/W) θJC (°C/W) QFN Package (Notes 1, 2). . . . . . . . . . 43 7 Maximum Junction Temperature (Note 3) . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C Recommended Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . +4.9V to +5.5V Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to 150°C junction may trigger the shutdown of the device even before 150°C since this number is specified as typical. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 3. Operation with die temperatures between +125°C and +150°C can be tolerated for short periods of time, however, in order to maximize the operating life of the IC, it is strongly recommended that the effective continuous operating junction temperature of the die should not exceed +125°C. Electrical Specifications PARAMETER Operating Conditions: VCC = 5V, TJ = -40°C to +85°C, unless otherwise specified TEST CONDITIONS MIN TYP MAX UNITS BIAS SUPPLY AND INTERNAL OSCILLATOR Input Bias Supply Current Rising VCC POR (Power-On Reset) Threshold VCC POR Hysteresis Rising PVCC POR Threshold Shunt Regulation Maximum Shunt Current Switching Frequency (per channel; Note 5) Frequency Tolerance Oscillator Peak-to-Peak Ramp Amplitude Maximum Duty Cycle CONTROL THRESHOLDS EN Threshold EN Hysteresis Current VMON Power-Good Enable Threshold VMON Hysteresis Current SOFT-START SS Current SS Ramp Amplitude SS Threshold for Output Gates Turn-Off REFERENCE AND DAC System Accuracy (Industrial Temp. Range) Internal Reference VREF -0.8 0.6 0.8 % V ISS 0.55 0.40 22 3.60 µA V V VVMON_TH 290 0.65 20 305 10 320 V µA mV µA VVCC; IVREG = 0 to 120mA IVREG_MAX FSW FSW VOSC dMAX IVCC; EN >0.7V; LG, UG open 4.30 0.46 3.60 4.90 120 150 -10 1.4 66 2000 10 7.6 4.40 0.51 3.67 5.10 9 4.50 0.58 3.75 5.35 mA V V V V mA kHz % V % 5 FN6352.1 October 18, 2006 ISL8121 Electrical Specifications PARAMETER External Reference DC Amplitude Range External Reference DC Offset Range ERROR AMPLIFIER AND REMOTE SENSING DC Gain (Note 4) Gain-Bandwidth Product (Note 4) Slew Rate (Note 4) Maximum Output Voltage Minimum Output Voltage VSEN+, VSEN- Input Resistance POWER GOOD PGD Rising Lower Threshold PGD Rising Upper Threshold PGD Threshold Hysteresis PROTECTION Overcurrent Trip Level Overvoltage Threshold Overvoltage Hysteresis SWITCHING TIME UG Rise Time (Note 4) LG Rise Time (Note 4) UG Fall Time (Note 4) LG Fall Time (Note 4) UG Turn-On Non-overlap (Note 4) LG Turn-On Non-overlap (Note 4) OUTPUT Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance NOTES: 4. Parameter magnitude guaranteed by design. 5. Not a tested parameter; range provided for reference only. 100mA Source Current 100mA Sink Current 100mA Source Current 100mA Sink Current 1.0 1.0 1.0 0.4 2.5 2.5 2.5 1.0 Ω Ω Ω Ω tRUG; VVCC = 5V, 3nF Load tRLG; VVCC = 5V, 3nF Load tFUG; VVCC = 5V, 3nF Load tFLG; VVCC = 5V, 3nF Load tPDHUG; VVCC = 5V, 3nF Load tPDHLG; VVCC = 5V, 3nF Load 8 8 8 4 8 8 ns ns ns ns ns ns VDIFF Rising VDIFF Falling 80 103 122 5.5 120 µA % % 92 112 2.5 % % % RL = 10K to ground CL = 10pF CL = 10pF No load No load 140 225 4.0 0.7 80 95 30 dB MHz V/µs V V kΩ VREFTRK (DC) VREFTRK (DC) offset Operat