Three-Phase Buck PWM Controller

® ISL8103 Data Sheet February 15, 2006 FN9246.0 Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers The ISL8103 is a three-phase PWM control IC with integrated MOSFET drivers. It provides a precision voltage regulation system for multiple applications including, but not limited to, high current low voltage point-of-load converters, embedded applications and other general purpose low voltage medium to high current applications.The integration of power MOSFET drivers into the controller IC marks a departure from the separate PWM controller and driver configuration of previous multi-phase product families. By reducing the number of external parts, this integration allows for a cost and space saving power management solution. Output voltage can be programmed using the on-chip DAC or an external precision reference. A two bit code programs the DAC reference to one of 4 possible values (0.6V, 0.9V, 1.2V and 1.5V). A unity gain, differential amplifier is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. The output voltage can also be offset through the use of single external resistor. An optional droop function is also implemented and can be disabled for applications having less stringent output voltage variation requirements or experiencing less severe step loads. A unique feature of the ISL8103 is the combined use of both DCR and rDS(ON) current sensing. Load line voltage positioning and overcurrent protection are accomplished through continuous inductor DCR current sensing, while rDS(ON) current sensing is used for accurate channel-current balance. Using both methods of current sampling utilizes the best advantages of each technique. Protection features of this controller IC include a set of sophisticated overvoltage and overcurrent protection. Overvoltage results in the converter turning the lower MOSFETs ON to clamp the rising output voltage and protect the load. An OVP output is also provided to drive an optional crowbar device. The overcurrent protection level is set through a single external resistor. Other protection features include protection against an open circuit on the remote sensing inputs. Combined, these features provide advanced protection for the output load. Features • Integrated Multi-Phase Power Conversion - 1, 2, or 3 Phase Operation • Precision Output Voltage Regulation - Differential Remote Voltage Sensing - ±0.8% System Accuracy Over Temperature (for REF=0.6V and 0.9V) - ±0.5% System Accuracy Over Temperature (for REF=1.2V and 1.5V) - Usable for Output Voltages not Exceeding 2.3V - Adjustable Reference-Voltage Offset • Precision Channel Current Sharing - Uses Loss-Less rDS(ON) Current Sampling • Optional Load Line (Droop) Programming - Uses Loss-Less Inductor DCR Current Sampling • Variable Gate-Drive Bias - 5V to 12V • Internal or External Reference Voltage Setting - On-Chip Adjustable Fixed DAC Reference voltage with 2-bit Logic Input Selects from Four Fixed Reference Voltages (0.6V, 0.9V, 1.2V, 1.5V) - Reference can be Changed Dynamically - Can use an External Voltage Reference • Overcurrent Protection • Multi-tiered Overvoltage Protection - OVP Pin to Drive Optional Crowbar Device • Selectable Operation Frequency up to 1.5MHz per Phase • Digital Soft-Start • Capable of Start-up in a Pre-Biased Load • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • High Current DDR/Chipset Core Voltage Regulators • High Current, Low Voltage DC/DC Converters • High Current, Low Voltage FPGA/ASIC DC/DC Converters Ordering Information PART NUMBER* ISL8103CRZ (Note) ISL8103IRZ (Note) ISL8103EVAL1 PART MARKING ISL8103CRZ ISL8103IRZ Evaluation Platform TEMERATURE (°C) 0 to 70 -40 to 85 PACKAGE 40 Ld 6x6 QFN (Pb-free) 40 Ld 6x6 QFN (Pb-free) PKG. DWG. # L40.6x6 L40.6x6 * Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8103 Pinout ISL8103 (6x6 QFN) TOP VIEW UGATE1 31 30 29 28 27 41 GND 26 25 24 23 22 21 11 VSEN 12 OCSET 13 ICOMP 14 DROOP 15 ISUM 16 IREF 17 LGATE3 18 PVCC3 19 ISEN3 20 UGATE3 BOOT1 PHASE1 PHASE2 UGATE2 BOOT2 ISEN2 PVCC2 LGATE2 PHASE3 BOOT3 LGATE1 PGOOD PVCC1 33 ISEN1 32 REF0 ENLL 37 REF1 OVP 40 3PH 2PH DAC REF OFST VCC COMP FB VDIFF RGND 1 2 3 4 5 6 7 8 9 10 39 38 FS 36 35 34 2 FN9246.0 February 15, 2006 ISL8103 Block Diagram ICOMP DROOP OCSET PGOOD OVP ENLL ISEN AMP ISUM IREF 100µA OC 0.66V POWER-ON RESET PVCC1 VCC RGND VSEN +1V BOOT1 UGATE1 GATE CONTROL LOGIC SHOOTTHROUGH PROTECTION SOFT-START x1 x1 AND FAULT LOGIC PHASE1 VDIFF LGATE1 UVP 0.2V OVP CLOCK AND SAWTOOTH GENERATOR PVCC2 BOOT2 UGATE2 FS OVP ∑ +150mV x 0.82 PWM1 GATE CONTROL LOGIC PWM2 SHOOTTHROUGH PROTECTION PHASE2 ∑ ∑ LGATE2 REF1 DAC REF0 DAC PWM3 CHANNEL DETECT 2PH 3PH PVCC3 BOOT3 REF FB E/A CHANNEL CURRENT BALANCE 1 N GATE CONTROL LOGIC SHOOTTHROUGH PROTECTION UGATE3 COMP PHASE3 ∑ OFFSET CHANNEL CURRENT SENSE OFST LGATE3 ISEN1 ISEN2 ISEN3 GND 3 FN9246.0 February 15, 2006 ISL8103 Typical Application - ISL8103 +12V VDIFF FB COMP PVCC1 BOOT1 VSEN RGND 3PH 2PH VCC UGATE1 PHASE1 ISEN1 LGATE1 +5V OFST +12V FS PVCC2 BOOT2 DAC UGATE2 ISL8103 REF PHASE2 ISEN2 LGATE2 REF1 REF0 OVP PGOOD +12V PVCC3 BOOT3 UGATE3 PHASE3 ISEN3 LGATE3 OCSET ICOMP ISUM LOAD +12V GND ENLL IREF DROOP 4 FN9246.0 February 15, 2006 ISL8103 Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V Absolute Boot Voltage, VBOOT . . . . . . . . GND - 0.3V to GND + 36V Phase Voltage, VPHASE . . . . . . . . GND - 0.3V to 15V (PVCC = 12) GND - 8V (<400ns, 20µJ) to 24V (<200ns, VBOOT-PHASE = 12V) Upper Gate Voltage, VUGATE . . . . VPHASE - 0.3V to VBOOT + 0.3V VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V Lower Gate Voltage, VLGATE. . . . . . . . GND - 0.3V to PVCC + 0.3V GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD Thermal Information Thermal Resistance θJA (°C/W) θJC (°C/W) QFN Package (Notes 1, 2) . . . . . . . . . . 32 3.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Recommended Operating Conditions VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature (ISL8103CRZ) . . . . . . . . . . . . . . 0°C to 70°C Ambient Temperature (ISL8103IRZ) . . . . . . . . . . . . . .-40°C to 85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER Recommended Operating Conditions, Unless Otherwise Specified. TEST CONDITIONS MIN TYP MAX UNITS BIAS SUPPLY AND INTERNAL OSCILLATOR Input Bias Supply Current Gate Drive Bias Current VCC POR (Power-On Reset) Threshold IVCC; ENLL = high IPVCC; ENLL = high; all gate outputs open, Fsw = 250kHz VCC Rising VCC Falling PVCC POR (Power-On Reset) Threshold PVCC Rising PVCC Falling Oscillator Ramp Amplitude (Note 3) Maximum Duty Cycle (Note 3) CONTROL THRESHOLDS ENLL Rising Threshold ENLL Hysteresis COMP Shutdown Threshold REFERENCE AND DAC System Accuracy (DAC = 0.6V, 0.9V) System Accuracy (DAC = 1.2V, 1.50V) DAC Input Low Voltage (REF0, REF1) DAC Input High Voltage (REF0, REF1) External Reference (Note 3) OFS Sink Current Accuracy (Negative Offset) OFS Source Current Accuracy (Positive Offset) ROFS = 30kΩ from OFS to VCC ROFS = 10kΩ from OFS to GND DROOP connected to IREF DROOP connected to IREF -0.8 -0.5 0.8 0.6 47.5 47.5 50.0 50.0 0.8 0.5 0.4 1.75 52.5 52.5 % % V V V µA µA COMP Falling 0.1 0.66 100 0.25 0.4 V mV V VPP 4.25 3.75 4.25 3.75 15 0.8 4.38 3.88 4.38 3.88 1.50 66.6 20 2.00 4.50 4.00 4.50 4.00 mA mA V V V V V % 5 FN9246.0 February 15, 2006 ISL8103 Electrical Specifications PARAMETER ERROR AMPLIFIER DC Gain (Note 3) Gain-Bandwidth Product (Note 3) Slew Rate (Note 3) Maximum Output Voltage Minimum Output Voltage REMOTE SENSE DIFFERENTIAL AMPLIFIER Input Bias Current (VSEN) Bandwidth (Note 3) Slew Rate (Note 3) OVERCURRENT PROTECTION OCSET Trip Current OCSET Accuracy ICOMP Offset PROTECTION Undervoltage Threshold Undervoltage Hysteresis Overvoltage Threshold while IC Disabled Overvoltage Threshold Overvoltage Hysteresis Open Sense-Line Protection Threshold OVP Output High Drive Voltage SWITCHING TIME UGATE Rise Time (Note 3