CCFL Brightness Controller

® ISL6884 Data Sheet March 9, 2006 FN9265.0 CCFL Brightness Controller ISL6884 controls Pulse Width Modulated Dimming for up to 8 inverters to supply power to up to 40 Cold Cathode Fluorescent Lamps (CCFL) for back lighting in large LCD displays. The ISL6884 brightness controller provides an I2C interface for dimming control, enable, status, and brightness balance. The duty cycle of all 8 DPWM outputs is adjusted with a Master Brightness Control register. The duty cycle of each of the 8 DPWM outputs can be offset from the master brightness to adjust for uniform brightness. The PWM dimming frequency can be set by an internal, adjustable oscillator or synchronized to an external source to minimize interference with video. ISL6884’s slave address is: • 1101_1111 for reading • 1101_1110 for writing Features • Wide Supply Voltage Range of 3.0V to 5.5V • Dimming - I2C dimming control input - PWM dimming can be synchronized to an external source or set by an internal, adjustable oscillator. - 8 channel dimming allows the user to balance the brightness of the CCFL lamps via I2C control - User programmable fault time out • User Programmable Fault Time Out • I2C Status Output • Pb-Free Plus Anneal Available (RoHS Compliant) Pinout ISL6884 (20 LD SSOP) TOP VIEW LAMP_ON 1 TESTEN 2 20 VDD 19 REGCAP 18 DPWM_8 17 DPWM_7 16 DPWM_6 15 DPWM_5 14 DPWM_4 13 DPWM_3 12 DPWM_2 11 DPWM_1 Ordering Information PART NUMBER ISL6884IAZ (See Note) ISL6884IAZ-T (See Note) TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 20 Ld SSOP (Pb-free) PKG. DWG. # M20.15 GNDPLL 3 PLL1 4 EN 5 DPWM_SYNC 6 OSCTEST 7 SCL 8 SDA 9 GND 10 20 Ld SSOP Tape M20.15 and Reel (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6884 Block Diagram VDD GND EN I2C ENABLE fault timer BGREF POR 2.5V REG REGCAP ENAB STATUS LAMP ON DPWM SYNC PLL1 GNDPLL PWM DIMMING PLL 8 CH DPWM GEN OSC DPWM_8 DPWM_7 DPWM_6 DPWM_5 DPWM_4 DPWM_3 DPWM_2 DPWM_1 8 BRIGHTNESS SDA SCL I2C interface STATUS ENABLE (I2C) TESTEN OSCTEST CCFL Brightness Controller 2 FN9265.0 March 9, 2006 ISL6884 Simplified System Diagram - Central Controller and Multiple Local Controllers ISL6884 CENTRAL CONTROLLER DPWM 4 DPWM 3 DPWM 2 DPWM 1 DPWM ISL6882 LOCAL CONTROLLER DRIVE IFB VFB PHASE MODULATION OUT DPWM ISL6882 LOCAL CONTROLLER DRIVE IFB VFB PHASE MODULATION OUT DPWM ISL6882 LOCAL CONTROLLER DRIVE IFB VFB PHASE MODULATION OUT SCL SDA SYSTEM I2C MASTER CCFL CCFL CCFL DRIVE ISL6883 DRIVER PM IN CCFL CCFL CCFL DRIVE ISL6883 DRIVER PM IN CCFL CCFL CCFL DRIVE ISL6883 DRIVER PM IN FI ON C EN D L IA T DPWM ISL6882 LOCAL CONTROLLER CCFL DRIVE IFB VFB CCFL CCFL DRIVE ISL6883 DRIVER PM IN PHASE MODULATION OUT 3 FN9265.0 March 9, 2006 ISL6884 ISL6884 Application Schematic external hardware enable LAMPON output from ISL6882 VDD LAMP_ON TESTEN GNDPLL PLL1 EN 1uF 2200 DPWM_SYNC OSCTEST SCL SDA GND 0.47uF 73.2K 0.1uF to the system master, other I2C devices and pull up resisters 1 2 3 4 5 7 8 9 10 20 19 18 17 16 14 13 12 11 VDD REGCAP DPWM_8 DPWM_7 DPWM_6 DPWM_5 DPWM_4 DPWM_3 DPWM_2 DPWM_1 Use these parts to adjust the internal DPWM oscillator frequency 3300 6 ISL6884 15 to DPWM dimming inputs to up to 8 ISL6882 This is the LPF for the DPWM PLL 1uF 1uF 0.01uF external signal to sync DPWM 4 FN9265.0 March 9, 2006 ISL6884 Absolute Maximum Ratings Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Input/Output Voltage . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Thermal Information Thermal Resistance (Typical, Notes 1) 20 Ld SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . θJA (°C/W) 110 Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40°C to 85°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% Thermal Information Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (SSOP - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER POWER ON RESET VDD Rising VDD Falling POR Hysteresis VOLTAGE REGULATOR Regulated Voltage Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PORrising PORfalling PORhyst 2.4 2.2 - 2.7 2.5 200 3.0 2.7 - V V mV Vreg External Capacitor = 1µF, ESR<1Ω 2.3 2.5 2.7 V LOGIC LEVEL INPUTS (EN, DPWM_SYNC, LAMPON) V In High V In Low Hysteresis Input Current VIHLOGIC VILLOGIC Vhyst I_IN Vin = VDD Vin = 0V I2 C V In Low V In High Schmitt Trigger Input Hysteresis V Out Low SDA, SCL Rise Time SDA, SCL Fall Time VIL VIH Vhys VOL Trise_I2C Tfall_I2C I in low = 3mA Cload = 200pF Rpullup = 1700, 30%-70% Cload = 200pF Rpullup = 1700, 30%-70% 0.7*VDD 0.05*VDD 300 0.3*VDD 0.4 300 V V V V ns ns 2.6 140 10 -10 0.8 V V mV nA nA 5 FN9265.0 March 9, 2006 ISL6884 Electrical Specifications PARAMETER DPWM DPWM PLL Free Run Frequency DPWM PLL Lock Frequency Lock Time DPWM Duty Cycle DPWM Duty Cycle DPWM Duty Cycle DPWM Output High DPWM Output Low DPWM Rise Time DPWM Fall Time NOTE: 2. Master enable (0X2B) = 01, channel enable (0X2C) = FF, all other registers in default mode ffreerun flock Tlock DPWMDCmin BRT_M = 00hex (Note 3) DPWMDCmid BRT_M = 7Fhex (Note 3) DPWMDCmax BRT_M = FFhex (Note 3) VOH VOL Trise_DPWM Tfall_DPWM IOH = 2mA IOL = 2mA Cload = 200pF Cload = 200pF 120 3 49 98 0.7*VDD 160 160 150 4 50 200 5 51 100 0.3*VDD 500 500 Hz Hz ms % % % V V ns ns Recommended Operating Conditions, Unless Otherwise Noted (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Pin Description VDD - Power input for digital systems. All functions are disabled unless this pin exceeds 3V (see Power On Reset specs). A 0.01µF decoupling cap should be placed between VDD and GND with the shortest possible traces. GND - Ground for digital systems. REGCAP - An external 1µF capacitor to decouple the internal 2.5V regulator. EN - Logic level input signal. Voltage at this pin above a threshold ENables circuit operation. DPWM SYNC - A logic level input signal. The dimming PWM frequency oscillator will synchronize to this signal (if present). If no signal is present at this pin, the internal DPWM oscillator will free run at approximately 160Hz. PLL1 - Analog input. An RC network on these pins sets the loop response of the DPWM Phase Locked Loop. A voltage source or resister divider at this pin will set the DPWM frequency. See the graph below for approximate frequency vs voltage at PLL1. 220 DPWM Frequency (Hz) 200 180 160 140 120 100 80 60 0.5 0.7 0.9 1.1 1.3 Voltage at PLL1 (V) F_DPWM=V_PLL1*160+8 measured GNDPLL - A separate ground terminal for the PLL. Filter and bias components on PLL1 should be connected to this ground with the shortest possible traces. This pin is also connected to the system ground with a trace that is not critical. DPWM 1:8 - Logic level outputs that control the analog and PWM dimming of each of 8 ISL6882s. The duty cycle of the DPWM signals range from 4% (minimum brightness) to 100% (maximum brightness). A low pass filter in the inverter Controller converts the DPWM duty cycle to a DC voltage that performs 3:1 analog dimming. The combined dimming range is 100:1. The dimming value is set by I2C registers. LAMP_ON - A logic level input signal. A high level on the pin indicates that all lamps are ON and operating normally. A low level at this pin indicates that at least one of the lamps is either not ignited or out of the circuit. When this pin is low, the fault timer runs. When this pin is high, the fault timer is reset. Because this is a high impedance line that may be routed near sources of EMI, it is recommended that a 10K resister is placed in series between the LAMP_ON pin and all other circuits. SDA, SCL - Logic level input/output signals. SDA is the I2C data line and SCL is the I2C clock line. The ISL6884 receives data via I2C to enable or disable the inverters, set dimming for each channel, and set the number of channels. System status can be read via I2C. TESTEN and OSCTEST - These pins are used for internal tests. They should be left unconnected in normal operation. 6 FN9265.0 March 9, 2006 ISL6884 I2C Register Description Register addresses and default values are given in the following Register Description Table. I2C Slave Address - ISL6884’s slave address is: • 1101_1111 for reading • 1101_1110 for writing BRT_M - Master Brightness Control input. This register controls the duty cycle of al 8 DPWM outputs. BRT_OS[1..8] - Brightness offset. These registers allow the system designer to increase or decrease the duty cycle of individual channel t