Synchronous Rectified MOSFET Driver

® ISL6609, ISL6609A Data Sheet March 6, 2006 FN9221.1 Synchronous Rectified MOSFET Driver The ISL6609, ISL6609A is a high frequency, MOSFET driver optimized to drive two N-Channel power MOSFETs in a synchronous-rectified buck converter topology. This driver combined with an Intersil ISL63xx or ISL65xx multiphase PWM controller forms a complete single-stage core-voltage regulator solution with high efficiency performance at high switching frequency for advanced microprocessors. The IC is biased by a single low voltage supply (5V), minimizing driver switching losses in high MOSFET gate capacitance and high switching frequency applications. Each driver is capable of driving a 3nF load with less than 10ns rise/fall time. Bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. The ISL6609, ISL6609A features 4A typical sink current for the lower gate driver, enhancing the lower MOSFET gate hold-down capability during PHASE node rising edge, preventing power loss caused by the self turn-on of the lower MOSFET due to the high dV/dt of the switching node. The ISL6609, ISL6609A also features an input that recognizes a high-impedance state, working together with Intersil multiphase PWM controllers to prevent negative transients on the controlled output voltage when operation is suspended. This feature eliminates the need for the schottky diode that may be utilized in a power system to protect the load from negative output voltage damage. In addition, the ISL6609A’s bootstrap function is designed to prevent the BOOT capacitor from overcharging, should excessively large negative swings occur at the transitions of the PHASE node. Features • Drives Two N-Channel MOSFETs • Adaptive Shoot-Through Protection • 0.4Ω On-Resistance and 4A Sink Current Capability • Supports High Switching Frequency - Fast Output Rise and Fall - Ultra Low Three-State Hold-Off Time (20ns) • ISL6605 Replacement with Enhanced Performance • BOOT Capacitor Overcharge Prevention (ISL6609A) • Low VF Internal Bootstrap Diode • Low Bias Supply Current • Enable Input and Power-On Reset • QFN Package - Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat No Leads-Product Outline - Near Chip-Scale Package Footprint; Improves PCB Efficiency and Thinner in Profile • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Core Voltage Supplies for Intel® and AMD® Microprocessors • High Frequency Low Profile High Efficiency DC/DC Converters • High Current Low Voltage DC/DC Converters • Synchronous Rectification for Isolated Power Supplies Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved. Intel® is a registered trademark of Intel Corporation. AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners. ISL6609, ISL6609A Ordering Information PART NUMBER (Note) ISL6609CBZ ISL6609CRZ ISL6609IBZ ISL6609IRZ ISL6609ACBZ ISL6609ACRZ ISL6609AIBZ ISL6609AIRZ PART MARKING ISL6609CBZ 609Z ISL6609IBZ 09IZ 6609ACBZ 09AZ 6609AIBZ 9AIZ TEMP. RANGE (°C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld 3x3 QFN 8 Ld SOIC 8 Ld 3x3 QFN 8 Ld SOIC 8 Ld 3x3 QFN 8 Ld SOIC 8 Ld 3x3 QFN PKG. DWG. # M8.15 L8.3x3 M8.15 L8.3x3 M8.15 L8.3x3 M8.15 L8.3x3 Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts ISL6609, ISL6609A (SOIC) TOP VIEW UGATE BOOT PWM GND 1 2 3 4 8 7 6 5 PHASE EN VCC LGATE BOOT 1 PWM 2 3 GND 4 LGATE 6 6 EN 5 VCC ISL6609, ISL6609A (QFN) TOP VIEW PHASE 7 UGATE 8 Block Diagram ISL6609 and ISL6609A RBOOT VCC EN VCC 4.25K PWM 4K CONTROL LOGIC SHOOTTHROUGH PROTECTION VCC LGATE GND BOOT UGATE PHASE INTEGRATED 3Ω RESISTOR (RBOOT) AVAILABLE ONLY IN ISL6609A 2 FN9221.1 March 6, 2006 ISL6609, ISL6609A Typical Application - Multiphase Converter Using ISL6609 Gate Drivers VIN +5V +5V +5V VCC EN PWM1 PWM2 PWM CONTROL (ISL63XX or ISL65XX) VID (OPTIONAL) ISEN1 ISEN2 +5V VIN PWM ISL6609 PHASE LGATE BOOT UGATE RUGPH FB VCC VSEN COMP PGOOD +VCORE FS/EN GND VCC EN PWM ISL6609 BOOT UGATE RUGPH PHASE LGATE RUGPH IS REQUIRED FOR SPECIAL POWER SEQUENCING APPLICATIONS (SEE APPLICATION INFORMATION SECTION ON PAGE 8) 3 FN9221.1 March 6, 2006 ISL6609, ISL6609A Absolute Maximum Ratings Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V BOOT Voltage (VBOOT-GND). . . -0.3V to 25V (DC) or 36V (<200ns) BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC) -0.3V to 9V (<10ns) PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC) GND -8V (<20ns Pulse Width, 10µJ) to 30V (<100ns) UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to 125°C HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Thermal Information Thermal Resistance (Notes 1, 2, 3) θJA(°C/W) θJC(°C/W) SOIC Package (Note 1) . . . . . . . . . . . . 110 N/A QFN Package (Notes 2, 3). . . . . . . . . . 95 36 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to 100°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. 3. θJC, “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details. Electrical Specifications PARAMETER VCC SUPPLY CURRENT Bias Supply Current POR Rising POR Falling Hysteresis PWM INPUT Sinking Impedance Source Impedance Three-State Rising Threshold Three-State Falling Threshold These specifications apply for TA = -40°C to 100°C, unless otherwise noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS IVCC PWM pin floating, VVCC = 5V 2.2 - 132 3.4 3.0 400 4.2 - µA mV RPWM_SNK RPWM_SRC VVCC = 5V (100mV Hysteresis) VVCC = 5V (100mV Hysteresis) tTSSHD tPDLU or tPDLL + Gate Falling Time 2.75 3 3.10 - 4 4.25 1.70 3.41 20 5.5 5.75 2.00 - kΩ kΩ V V ns Three-State Shutdown Holdoff Time EN INPUT EN LOW Threshold EN HIGH Threshold SWITCHING TIME (See Figure 1 on Page 6) UGATE Rise Time (Note 4) LGATE Rise Time (Note 4) UGATE Fall Time (Note 4) LGATE Fall Time (Note 4) UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay 1.0 - 1.3 1.6 2.0 V V tRU tRL tFU tFL tPDLU tPDLL VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded - 8.0 8.0 8.0 4.0 18 25 - ns ns ns ns ns ns 4 FN9221.1 March 6, 2006 ISL6609, ISL6609A Electrical Specifications PARAMETER UGATE Turn-On Propagation Delay LGATE Turn-On Propagation Delay Three-state to UG/LG Rising Propagation Delay OUTPUT Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance NOTE: 4. Guaranteed by Characterization. Not 100% tested in production. RUG_SRC RUG_SNK RLG_SRC RLG_SNK 250mA Source Current 250mA Sink Current 250mA Source Current 250mA Sink Current 1.0 1.0 1.0 0.4 2.5 2.5 2.5 1.0 Ω Ω Ω Ω These specifications apply for TA = -40°C to 100°C, unless otherwise noted (Continued) SYMBOL tPDHU tPDHL tPTS TEST CONDITIONS VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded MIN TYP 18 23 20 MAX UNITS ns ns ns Functional Pin Description Note: Pin numbers refer to the SOIC package. Check diagram for corresponding QFN pinout. LGATE (Pin 5) Lower gate drive output. Connect to gate of the low side N-Channel power MOSFET. A gate resistor is never recommended on this pin, as it interferes with the operation shoot-through protection circuitry. UGATE (Pin 1) Upper gate drive output. Connect to gate of high-side N-Channel power MOSFET. A gate resistor is never recommended on this pin, as it interf