Step-Down PWM and Single Linear Controller

® ISL6441 Data Sheet October 4, 2005 FN9197.1 1.4MHz Dual, 180° Out-of-Phase, StepDown PWM and Single Linear Controller The ISL6441 is a high-performance, triple-output controller optimized for converting wall adapter, battery or network intermediate bus DC input supplies into the system supply voltages required for a wide variety of applications. Each output is adjustable down to 0.8V. The two PWMs are synchronized 180o out of phase reducing the RMS input current and ripple voltage. The ISL6441 incorporates several protection features. An adjustable overcurrent protection circuit monitors the output current by sensing the voltage drop across the lower MOSFET. Hiccup mode overcurrent operation protects the DC/DC components from damage during output overload/short circuit conditions. Each PWM has an independent logic-level shutdown input (SD1 and SD2). A single PGOOD signal is issued when soft-start is complete on both PWM controllers and their outputs are within 10% of the set point and the linear regulator output is greater than 75% of its setpoint. Thermal shutdown circuitry turns off the device if the junction temperature exceeds +150°C. Features • Wide Input Supply Voltage Range - 5.6V to 24V - 4.5V to 5.6V • Three Independently Programmable Output Voltages • Switching Frequency . . . . . . . . . . . . . . . . . . . . . . .1.4MHz • Out of Phase PWM Controller Operation - Reduces Required Input Capacitance and Power Supply Induced Loads • No External Current Sense Resistor - Uses Lower MOSFET’s rDS(ON) • Bi-directional Frequency Synchronization for Synchronizing Multiple ISL6441s • Programmable Soft-Start • Extensive Circuit Protection Functions - PGOOD - UVLO - Overcurrent - Overtemperature - Independent Shutdown for Both PWMs • Excellent Dynamic Response - Voltage Feed-Forward with Current Mode Control • QFN Package: - QFN - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile • Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NUMBER ISL6441IR PART MARKING ISL6441IR TEMP. RANGE (°C) -40 to 85 -40 to 85 PACKAGE 28 Ld QFN 28 Ld QFN (Pb-free) PKG. DWG. # L28.5x5 L28.5x5 ISL6441IRZ ISL6441IRZ (See Note) Add “-T” or “-TK” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Applications • Power Supplies with Multiple Outputs • xDSL Modems/Routers • DSP, ASIC, and FPGA Power Supplies • Set-Top Boxes • Dual Output Supplies for DSP, Memory, Logic, µP Core and I/O • Telecom Systems 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6441 Pinout ISL6441 (QFN) TOP VIEW PHASE1 22 21 ISEN1 20 PGND 19 SD1 18 SS1 17 SGND 16 OCSET1 15 FB1 8 FB2 9 SGND 10 VIN 11 SYNC 12 FB3 13 GATE3 14 SGND UGATE2 UGATE1 23 LGATE2 LGATE1 25 BOOT2 BOOT1 24 28 PHASE2 ISEN2 PGOOD VCC_5V SD2 SS2 OCSET2 1 2 3 4 5 6 7 27 26 2 FN9197.1 October 4, 2005 Block Diagram BOOT1 UGATE1 PHASE1 VCC_5V LGATE1 PGND ADAPTIVE DEAD-TIME DIODE EMULATION V/I SAMPLE TIMING ADAPTIVE DEAD-TIME DIODE EMULATION V/I SAMPLE TIMING PGOOD SD1 VIN SGND SD2 VCC BOOT2 UGATE2 PHASE2 VCC LGATE2 POR PGND ENABLE 0.8V REFERENCE BIAS SUPPLIES REFERENCE FAULT LATCH SOFT-START UV PGOOD UV PGOOD 3 GATE3 gm*VE + VE + - FB3 ISL6441 800kΩ FB1 180kΩ 18.5pF 18.5pF 800kΩ + 16kΩ OC1 OC2 PWM2 + 16kΩ ERROR AMP 2 180kΩ VSEN2 + PWM1 + SOFT2 + 0.9V REF SS1 ERROR AMP 1 + DUTY CYCLE RAMP GENERATOR PWM CHANNEL PHASE CONTROL 0.8V REF ISEN2 ISEN1 CURRENT SAMPLE CURRENT SAMPLE + CURRENT SAMPLE + CURRENT SAMPLE OCSET1 OCSET2 + 0.8V REFERENCE 0.8V REFERENCE + + OC1 OC2 + VIN SAME STATE FOR 2 CLOCK CYCLES REQUIRED TO LATCH OVERCURRENT FAULT VCC SAME STATE FOR 2 CLOCK CYCLES REQUIRED TO LATCH OVERCURRENT FAULT FN9197.1 October 4, 2005 ISL6441 Typical Application Schematic 4 FN9197.1 October 4, 2005 ISL6441 Absolute Maximum Ratings Supply Voltage (VCC_5V Pin) . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Input Voltage (VIN Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+27V BOOT1, 2 and UGATE1, 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . +35V PHASE1, 2 and ISEN1, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27V BOOT1, 2 with Respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . +6.5V UGATE1, 2. . . . . . . . . . . . (PHASE1, 2 - 0.3V) to (BOOT1, 2 +0.3V) Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 28 Lead QFN (Note 1) . . . . . . . . . . . 36 5.5 Maximum Junction Temperature (Plastic Package) . -55°C to 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJC is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. For θJA the “case temp” location is the center of the exposed metal pad on the underside of the package. See Tech Brief TB379. Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to 85°C (Note 2), Typical values are at TA = 25°C TEST CONDITIONS MIN TYP MAX UNITS PARAMETER VIN SUPPLY Input Voltage Range VCC_5V SUPPLY (Note 3) Input Voltage Output Voltage Maximum Output Current SUPPLY CURRENT Shutdown Current (Note 4) Operating Current (Note 5) REFERENCE SECTION Nominal Reference Voltage Reference Voltage Tolerance POWER-ON RESET Rising VCC_5V Threshold Falling VCC_5V Threshold OSCILLATOR Total Frequency Variation Peak-to-Peak Sawtooth Amplitude (Note 6) 5.6 12 24 V VIN = VCC_5V VIN > 5.6V, IL = 20mA VIN = 12V 4.5 4.5 60 5.0 5.0 - 5.6 5.5 - V V mA SD1 = SD2 = GND - 50 2.0 375 4.0 µA mA -1.0 0.8 - 1.0 V % 4.25 3.95 4.45 4.2 4.5 4.4 V V 1.25 VIN = 12V VIN = 5V 5.1 3.5 10 VCC - 0.6V 1.4 1.5 0.625 1.0 5.6 - 1.55 10.0 6.2 1.5 - MHz V V V ns MHz V V ns V Ramp Offset (Note 7) SYNC Input Rise/Fall Time (Note 7) SYNC Frequency Range SYNC Input HIGH Level SYNC Input LOW Level SYNC Input Minimum Pulse Width (Note 7) SYNC Output HIGH Level 5 FN9197.1 October 4, 2005 ISL6441 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to 85°C (Note 2), Typical values are at TA = 25°C (Continued) TEST CONDITIONS MIN TYP MAX UNITS PARAMETER SHUTDOWN1/SHUTDOWN2 HIGH Level (Converter Enabled) LOW Level (Converter Disabled) PWM CONVERTERS Output Voltage FB Pin Bias Current Maximum Duty Cycle Internal Pull-up (3µA) 2.0 - - 0.8 V V PWM1, COUT = 1000p, TA = 25°C PWM2, COUT = 1000pF, TA = 25°C 71 73 - 0.8 4 150 - V nA % % % Minimum Duty Cycle PWM CONTROLLER ERROR AMPLIFIERS DC Gain (Note 7) Gain-Bandwidth Product (Note 7) Slew Rate (Note 7) Maximum Output Voltage (Note 7) Minimum Output Voltage (Note 7) PWM CONTROLLER GATE DRIVERS (Note 8) Sink/Source Current Upper Drive Pull-Up Resistance Upper Drive Pull-Down Resistance Lower Drive Pull-Up Resistance Lower Drive Pull-Down Resistance Rise Time Fall Time LINEAR CONTROLLER Drive Sink Current FB3 Feedback Threshold Undervoltage Threshold FB3 Input Leakage Current Amplifier Transconductance POWER GOOD AND CONTROL FUNCTIONS PGOOD LOW Level Voltage PGOOD Leakage Current PGOOD Upper Threshold, PWM 1 and 2 PGOOD Lower Threshold, PWM 1 and 2 PGOOD for Linear Controller Fraction of set point Fraction of set point Pull-up = 100kΩ VFB = 0.8V, I = 21mA I = 21mA VFB VCC_5V = 4.5V VCC_5V = 4.5V VCC_5V = 4.5V VCC_5V = 4.5V COUT = 1000pF COUT = 1000pF 80 5.9 0.9 - 88 2.0 - 3.6 dB MHz V/µs V V - 400 8 3.2 8 1.8 18 18 - mA ns ns 50 - 0.8 75 45 2 150 - mA V % nA A/V 105 80 70 0.1 75 0.5 ±1.0 120 95 80 V µA % % % 6 FN9197.1 October 4, 2005 ISL6441 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to 85°C (Note 2), Typical values are at TA = 25°C (Continued) TEST CONDITIONS MIN TYP MAX UNITS PARAMETER ISEN and CURRENT LIMIT Full Scale Input Current (Note 9) Over-Current Threshold (Note 9) OCSET (Current Limit) Voltage SOFT-START Soft-Start Current PROTECTION Thermal Shutdown Rising ROCSET = 110kΩ - 32 64 1.75 - µA µA V - 5 - µA - 150 20 - °C °C Hysteresis NOTES: 2. Specifications at -40°C and 85°C are guaranteed by design, not production tested. 3. In normal operation, where the device is supplied with voltage on the VIN pin, the VCC_5V pin provides a 5V output capable of 60mA (min). When the VCC_5V pin is used as a 5V supply input, the internal LDO regulator is disabled and the VIN input pin must be connected to the VCC_5V pin. (Refe