FlexiHash

N E SI G EW D N ® FO R DED 9206 LE M EN L COM USE IS MPATIB O T RE C NO Data IN OR-P Sheet I N- F P S ISL6296 January 17, 2007 FN9201.1 FlexiHash™ For Battery Authentication The ISL6296 is a highly cost-effective fixed-secret hash engine based on Intersil’s FlexiHash™ technology. The device authentication is achieved through a challengeresponse scheme customized for low-cost applications, where cloning via eavesdropping without knowledge of the device’s secret code is not economically viable. When used for its intended applications, the ISL6296 offers the same level of effectiveness as other significantly more expensive high maintenance monetary-grade hash algorithm and authentication schemes. The ISL6296 has a wide operating voltage range, and is suitable for direct powering from a 1-cell Li-Ion/Li-Poly or a 3-cell series NiMH battery pack. The ISL6296 can also be powered by the XSD bus when the bus pull-up voltage is 3.3V or higher. The device connects directly to the cell terminals of a battery pack, and includes on-chip voltage regulation circuit, POR, and a non-crystal based oscillator for bus timing reference. Communication with the host is achieved through a singlewire XSD interface - a light-weight subset of Intersil’s ISD bus interface. The XSD bus is compatible for use with serial ports offered by all 8250 compatible UART’s or a single GPIO (general purpose input and output) pin of a microprocessor. A clone prevention solution utilizing the ISL6296 offers safety and revenue protection at the lowest cost and power, and is suitable for protection against after-market replacement for a wide variety of low-cost applications. Features • Challenge-response based authentication scheme using 32-Bit challenge code and 8-Bit authentication code. • Fast and flexible authentication process. Multi-pass authentication can be used to achieve the highest security level if necessary. • 16x8 OTP ROM stores up to three sets of 32-Bit hostselectable secrets with additional programmable memory for storage of up to 48 bits of ID code and/or pack information. • FlexiHash engine uses two sets of 32-Bit secrets for authentication code generation. • Non-unique mapping of the secret key to an 8-Bit authentication code maximizes hacking difficulty due to need for exhaustive key search (superior to SHA-1). • Supports 1-cell Li-Ion/Li-Poly and 3-cell series NiMH battery packs (2.6V ~ 4.8V operation), or powered by the XSD bus. • XSD single-wire host bus interface communicates with all 8250-compatible UART’s or a single GPIO. Supports CRC on read data and transfer bit-rate up to 23kbps. • True “Zero Power” Sleep mode - automatically entered after a bus inactivity time-out period • 5 Ld SOT-23 and 8 Ld TDFN (2mm x 3mm) packages • -20°C to +85°C operating temperature range • Pb-free plus anneal available (RoHS compliant) Pinouts ISL6296 (5 LD SOT-23) TOP VIEW VSS 1 N/C 2 VDD 3 4 TIO 5 XSD Applications • Battery Pack Authentication • Printer Cartridges • Add-on Accessories • Other Non-Monetary Authentication Applications Related Literature • Application Note AN1165 “ISL6296 Evaluation Kit” ISL6296 (8 LD 2X3TDFN) TOP VIEW VSS NC NC VDD 1 2 3 4 8 7 6 5 XSD NC NC TIO • Application Note AN1166 “FlexiHash™ Engine Algorithm” • Application Note AN1167 “Implementing XSD Host Using a GPIO” • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) ” 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved. FlexiHash is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. ISL6296 Ordering Information PART NUMBER (Note) ISL6296DHZ-T ISL6296DRZ-T PART MARKING 296Z 96Z TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # P5.064 -20 to +85 5 Ld SOT-23 Tape and Reel -20 to +85 8 Ld 2x3 TDFN Tape and Reel L8.2X3A ISL6296EVAL1 ISL6296 Evaluation Kit NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN9201.1 January 17, 2007 ISL6296 Absolute Maximum Ratings (Reference to GND) Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to VDD+0.5V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . .4000V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .400V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000V Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) SOT-23 Package (Note 1) . . . . . . . . . . 200 N/A 2x3 TDFN Package (Notes 2, 3) . . . . . 70 10.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C Maximum Storage Temperature Range . . . . . . . . . .-40°C to +125°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-20°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER DC CHARACTERISTICS Supply Voltage Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -20°C to +85°C; VDD = 2.6V to 4.8V. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VDD During normal operation During OTP ROM programming 2.6 2.8 2.3 11 1.9 1.5 110 120 0.15 250 2.5 12 2.2 1.8 4.8 4.8 140 160 0.5 500 2.7 13 2.4 2.1 V V μA μA μA μA V V V V Run Mode Supply Current (exclude I/O current) Sleep Mode Supply Current OTP Programming Mode Supply Current Internal Regulated Supply Voltage Internal OTP ROM Programming Voltage POR Release Threshold POR Assertion Threshold XSD PIN CHARACTERISTICS XSD Input Low Voltage XSD Input High Voltage XSD Input Hysteresis XSD Internal Pull-Down Current IDD VDD = 4.2V VDD = 4.8V IDDS IDDP VRG VPP VPOR+ VPOR- VDD = 4.2V, XSD pin floating For ~ 1.8ms duration per write operation Observable only in test mode Observable only in test mode VIL VIH VHYS IPD VDD = 2.6V VDD = 4.2V VDD = 4.8V -0.4 1.5 - 400 0.8 1.2 1.8 6 0.5 VDD+ 0.4V 2.0 2.5 0.4 2 50 - V V mV μA μA μA V μs ns pF XSD Output Low Voltage XSD Input Transition Time XSD Output Fall Time XSD Pin Capacitance VOL tX tF CPIN IOL = 1mA 10% to 90% transition time 90% to 10%, CLOAD = 12pF XSD BUS TIMING CHARACTERISTICS (Refer to XSD Bus Symbol Timing Definitions Tables) Programming Bit Rate XSD Input Deglitch Time TWDG x = 0.5 to 4 Pulse width narrower than the deglitch time will not cause the device to wake up 2.89 7 23.12 20 kHz μs 3 FN9201.1 January 17, 2007 ISL6296 Electrical Specifications PARAMETER Device Wake-Up Time Device Sleep Wait Time Auto-Sleep Time-Out Period OTP ROM Write Time Hash Calculation Time Soft-Reset Time Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -20°C to +85°C; VDD = 2.6V to 4.8V. (Continued) SYMBOL TWKE TSLP TASLP TEEW THASH TSRST TEST CONDITIONS From falling-edge of break command issued by host to falling-edge of break command returned by device From when the ‘11’ Opcode is detected to the shut-off of the internal regulator From the last transition detected on the XSD bus to the device going into sleep mode From the last BT of the 2nd write data frame to when device is ready to accept the next instruction From the last BT of the Challenge Code Word from the host to the Authentication Code being available for read From the last BT of the Soft-Reset instruction issued by the host to the falling-edge of break command returned by device MIN 35 4 0.9 TYP 60 1.8 1 MAX 100 1.1 1.9 30 UNITS μs μs s ms BT μs AC CHARACTERISTICS Oscillator Clock Frequency Charge Pump Clock Frequency fOSC fCP Internal bus reference clock Internal high speed clock (observable only in test mode) Low-speed mode High-speed mode 3.6 16 5 20 6 24 MHz MHz 505 532 560 kHz Pin Descriptions PIN NUMBER 1 2 3 4 5 PIN NAME VSS NC VDD TIO XSD System ground. No connection. Supply voltage. Production test I/O pin. Used only during production testing. Must be left floating during normal operation. Communication bus with weak internal pull-down to VSS. This pin is a Schmitt-trigger input and an open-drain output. An appropriate pull-up resistor is required on the host side. DESCRIPTION 4 FN9201.1 January 17, 2007 ISL6296 Typical Applications PACK+ R1 100Ω XSD D1 5.1V PACKR2 100Ω PROTECTION C1 0.1µF XSD ISL9269 VSS VDD FIGURE 1. TYPICAL APPLICATION WITH THE ISL6296 POWERED BY THE BATTERY PACK+ R1 100Ω XSD D1 5.1V PACK- XSD ISL9269 VSS VDD C1 0.1µF PROTECTION FIGURE 2. TYPI