Integrated XScale Regulator

® ISL6271A Data Sheet October 8, 2004 FN9171.1 Integrated XScale Regulator The ISL6271A is a versatile power management IC (PMIC) designed for the Xscale type of processors. The device integrates three regulators, two fault indicators and an I2C bus for communication with a host microprocessor. Two of the three regulators function as low power, low drop out regulators, designed to power SRAM and phase-lock loop circuitry internal to the Xscale processor. The third regulator uses a proprietary switch-mode topology to power the processor core and facilitate Dynamic Voltage Management (DVM), as defined by Intel. Since power dissipation inside a microprocessor is proportional to the square of the core voltage, Intel XScale processors implement DVM as a means to more efficiently utilize battery capacity. To support this power saving architecture, the ISL6271A integrates an I2C bus for communication with the host processor. The processor, acting as the bus master, transmits a “voltage level” and “voltage slew rate” to the ISL6271A appropriate to the processing requirements; higher core voltages support higher operating frequencies and code execution. The bus is fully compliant with the Phillips® I2C protocol and supports both standard and fast data transmission modes. Alternatively, the output of the core regulator can be programmed in 50mV increments from 0.85V to 1.6V using the input Voltage ID (VID) pins. All three regulators share a common enable pin and are protected against overcurrent, over temperature and undervoltage conditions. When disabled via the enable pin, the ISL6271A enters a low power state that can be used to conserve battery life while maintaining the last programmed VID code and slew rate. An integrated soft-start circuit transitions the ISL6271A output voltages to their default values at a rate determined by an external soft-start capacitor. Features • Three Voltage Regulators (1 Buck, 2 LDOs) • High-Efficiency, fully-Integrated synchronous buck regulator with DVM • 800mA DC output current for the buck regulator • Proprietary ‘Synthetic Ripple’ Control Topology • Greater than 1MHz Switching Frequency • Diode emulation for light load efficiency • I2C Interface Module for DVM from 0.85V to 1.6V • Optional fixed 4-bit VID-control in lieu of DVM • Small Output Inductor and Capacitor • Battery Fault signal • Input Supply Voltage Range: 2.76V-5.5V • 4x4 mm QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile • Pb-free Available (RoHS Compliant) Applications • PDA • Cell Phone • Tablet Devices • Embedded Processors Related Literature • Technical Brief TB379 “Thermal Characterization of Packaged Semiconductor Devices” • Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages“ Pinout ISL6271A (4x4 QFN) TOP VIEW BFLT# BBAT SOFT GND EN • Application Note AN1139 “Setup Instruction for the ISL6271 Evaluation Kit” 20 VCC VIDEN SCL/VID0 SDA/VID1 VID2 1 2 3 4 5 6 VID3 19 18 17 16 15 LVCC 14 VPLL 13 VSRAM 12 FB 11 VOUT Ordering Information PART NUMBER* ISL6271ACR ISL6271ACRZ (Note) TEMP. RANGE (°C) -25 to 85 -25 to 85 PACKAGE 20 Ld 4x4 QFN 20 Ld 4x4 QFN (Pb-free) PKG. DWG. # L20.4x4 L20.4x4 *Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 7 PGND 8 PHASE 9 PVCC 10 PGOOD 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004. All Rights Reserved Intel® is a registered trademark of Intel Corporation. All other trademarks mentioned are the property of their respective owners. ISL6271A Regulator Block Diagram LVCC LDO1 VSRAM (VCC_SRAM) EN LDO2 PVCC SCL (VID 0) SDA (VID 1) VID2 VID3 VIDEN VPLL (VCC_PLL) I2C & STATIC VID LOGIC DAC SWITCHING REGULATOR VOUT (VCC_VCORE) FIGURE 1. BULVERDE POWER CONTROLLER Functional Block Diagram VIDEN PGOOD BFLT# BBAT VCC 1.1V VSRAM 1.3V VPLL LVCC PVCC OVERCURRENT DETECT CIN 1.8V TO 5.5V SCL/VID0 SDA/VID1 VID2 VID3 I2C OV UV OT POR TEMP MONITOR LDO1 AND LDO2 2.6V TO 5.5V DAC VOUT VCC_CORE MONITOR OV UV + CMP GATE DRIVE LOGIC EN SOFT CSS FB + - GATE DRIVE & ZERO CURRENT DETECT Lo PHASE VOUT COUT ERROR AMP C RP RC CC RIPPLE AMP PGND + 50Ω RRP GND RING DAMPING CIRCUIT VOUT RCOMP FIGURE 2. FUNCTIONAL BLOCK DIAGRAM 2 FN9171.1 ISL6271A Absolute Maximum Ratings (PVCC, VCC, LVCC) to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V PHASE to PGND . . . . . . . . . . . . . . . . . . . . . .-0.3V to (PVCC +0.3V) PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V All other pins to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .2kV Thermal Information Thermal Resistance. . . . . . . . . . . . . . . . . θJA (°C/W) θJC (°C/W) 4x4 QFN Package (Notes 1, 2) . . . . 45 7.5 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-25°C to 85°C Supply Voltage (PVCC, VCC) . . . . . . . . . . . . . . . . . . . . 2.76 to 5.5V Supply Voltage (LVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 - 5.5V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features (TB379). 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER CORE BUCK REGULATOR Input Voltage Range (After VCC reaches Rising VPOR) Output Voltage Nominal Range Max. DC Output Current Current Limit (DC plus Ripple) PMOS on Resistance NMOS on Resistance Frequency (Note 4) Load Regulation Line Regulation VOUT Pk-Pk Ripple VP-P PVCC VOUT Icore Icore_lim rDS(ON)p rDS(ON)n f PVCC = VCC Programmable in 50mV increments (Note 3) (wafer level test only) Iout = 200mA Iout = 200mA Vin = 3.7V, Vo = 1.0V, VF6 = 0.9V VOUT = 1.6V; Io = 1mA-500mA Over VCC range Vout = 1.6V, I = 0.4A, CCM Discontinous Mode Operation System Accuracy Under Voltage Threshold (Note 5) Over Temperature Room Temperature Rising, as % of nominal VOUT Falling, as % of nominal VOUT Over Voltage threshold Rising, as % of nominal VOUT Falling, as % of nominal VOUT Start-up Time Ring Damping Switch Resistance LINEAR REGULATORS Input Voltage LVCC Connected to PVCC Not connected to PVCC Output Voltage VSRAM VPLL 2.76 1.70 1.1 1.3 5.5 3.5 V V V V tst Ron(RD) From Enable Active @ Io = 10mA; Vo = 1.6V -1 -1 94 86 114 106 1.3 50 75 2.76 0.85 800 950 1300 275 140 1.2 .05 1 5 10 2 1 1 5.5 1.60 V V mA mA mΩ mΩ MHz % % mV mV % % % % % % ms Ω Operating Conditions, Unless Otherwise Noted; TA = -25°C to 85°C, PVCC = VCC = 3.7V. Component values as shown in Figure 19, Typical Application Circuit: Vout = 1.6V, IOUT = 0mA SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 3 FN9171.1 ISL6271A Electrical Specifications PARAMETER Output Tolerance Maximum Average Output Current I_SRAM I_PLL Current Limit Line Regulation Load Regulation Undervoltage Threshold Ildo_lim Each LDO regulator LVCC = 1.7-5.5V Io = 1 to 25mA Rising - % of VPLL, VSRAM Falling - % of VPLL, VSRAM Start-Up Time SYSTEM Supply Current (VCC) IQ IQ Supply Current (LVCC) EN Voltage ILVCC VIH VIL Soft-Start Source Current (Controlled by I2C control bits D5, D4) I00 I01 I10 I11 Temperature Shutdown Tr Tf POR/BFLT# Threshold (Note 6) VPOR VPOR PGOOD Pull Down Resistance VIDEN, VID2, VID3 Voltage Threshold Ron VIH(VID) VIL(VID) I2C LOGIC SCL, SDA Voltage Threshold VIH(I2C) VIL(I2C) SDA Pull Down Resistance NOTES: 3. Guaranteed by design; correlated with statistic data for PVCC = VCC from 3.5V to 5.5V. 4. Switching frequency is a function of input, output voltage and load. 5. As a result of an over-current condition exceeding 800mA. Will result in a PGOOD fault. 6. A high rising POR tracks with a high falling POR. 7. Percentage of Maximum Average Output Current (I_SRAM or I_PLL). Ron(SDA) 2.0 0.55 132 V V Ω 2.4 1.0 Rising T Falling T Rising VCC Falling VCC 3.4 6.7 16 30 130 85 2.60 2.44 4.8 9.6 24 47 140 95 2.80 2.60 700 2.0 0.55 6.2 12.5 32 64 150 105 3.0 2.76 960 Icore = No load EN = 0V 380 2 25 5 µA µA µA V V µA µA µA µA °C °C V V Ω V V tst Operating Conditions, Unless Otherwise Noted; TA = -25°C to 85°C, PVCC = VCC = 3.7V. Component values as shown in Figure 19, Typical Application Circuit: Vout = 1.6V, IOUT = 0mA (Continued) SYMBOL Iout = 1mA TEST CONDITIONS MIN -2.5 50 40 120 300 0.25 .5 91 86 1.3 TYP MAX 2.5 UNITS % mA mA % (Note 7) % % % % ms Soft-start power up to 1.3V, Csoft = 10nF 4 FN9171.1 ISL6271A Typical Operating Performance Test results from the Intersil ISL6271A Customer Reference Board (CRB). Output filter on switcher made up of a 4.7µH drumcore with 100mΩ of DCR and an output capaci