(ISL6123 - ISL6130) Power Sequencing Controllers

® ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 Data Sheet February 5, 2007 FN9005.8 Power Sequencing Controllers The Intersil ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128 and ISL6130 are integrated four channel controlled-on/controlled-off power-supply sequencers with supply monitoring, fault protection and a “sequence completed” signal (RESET#). For larger systems, more than four supplies can be sequenced by simply connecting a wire between SYSRESET# pins of cascaded IC's. The ISL6125 uses four open-drain outputs to control the on/off sequencing of four supplies, while the other sequencers use a patented, micropower 7X charge pump to drive four external low-cost NFET switch gates above the supply rail by 5.3V. These IC's can be biased from any supply 5V down to 1.5V. Individual product descriptions follow. The four channel ISL6123 (ENABLE input), ISL6124 (ENABLE# input) and ISL6125 ICs offer the designer 4 rail control when it is required that all four rails are in minimal compliance prior to turn on and that compliance must be maintained during operation. The ISL6123 and ISL6130 have a low power standby mode when disabled, suitable for battery powered applications. www.DataSheet4U.com Features • Enables arbitrary turn-on and turn-off sequencing of up to four power supplies (0.7V to 5V) • Operates from 1.5V to 5V supply voltage • Supplies VDD +5.3V of charge pumped gate drive • Adjustable voltage slew rate for each rail • Multiple sequencers can be daisy-chained to sequence an infinite number of independent supplies • Glitch immunity • Under voltage lockout for each supply • 1µA Sleep State (ISL6123, ISL6130) • Active high (ISL6123, ISL6130) or low (ISL6124, ISL6125, ISL6126, ISL6127, ISL6128) ENABLE# input • Open drain version available (ISL6125) • Voltage Determined Sequence (ISL6126, ISL6130) • Pre-programmed Sequence available (ISL6127) • Dual channel groupings (ISL6128) • QFN package with Pb-free plus anneal option (RoHS compliant) The ISL6125 operates like the ISL6124 but instead of charge pump driven gate drive outputs it has open drain logic outputs for direct interface to other circuitry. In contrast to the majority, for both the ISL6126 and ISL6130 each of the four channels operates independently so that the various GATEs will turn on once its individually associated input voltage requirements are met. The ISL6127 is a pre programmed A-B-C-D turn-on and D-C-B-A turn-off sequenced IC. Once all inputs are in compliance and ENABLE is asserted the sequencing starts and each subsequent GATE will turn-on after the previous one completes turning-on. The ISL6128 has two groups of two channels each with its independent I/O and is ideal for voltage sequencing into redundant capability loads as all four inputs need to be satisfied prior to turn on but a single group fault is ignored by the other group. External resistors provide flexible voltage threshold programming of monitored rail voltages. Delay and sequencing are provided by external capacitors for both ramp up and ramp down. Additional I/O is provided indicating and driving RESET state in various configurations. For volume applications, other programmable options and features can be had. Contact the factory with your needs. Applications • Graphics cards • FPGA/ASIC/microprocessor/PowerPC supply sequencing • Network routers • Telecommunications systems Pinout ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 (24 LD QFN) TOP VIEW DLY_ON_A SYSRST# UVLO_A 20 RESET# VDD 24 ENABLE/ ENABLE# GATE_A DLY_OFF_C DLY_OFF_D GATE_B GATE_C 1 2 3 23 22 21 19 18 DLY_OFF_A 17 UVLO_C 16 DLY_ON_C 4mmx4mm 4 5 6 7 GATE_D 8 DLY_ON_B 9 NC 10 GND 11 NC 12 UVLO_B 15 DLY_ON_D 14 UVLO_D 13 DLY_OFF_B 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001, 2003-2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. NC ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 Ordering Information PART NUMBER* ISL6123IR ISL6124IR ISL6125IR ISL6126IR ISL6127IR ISL6128IR ISL6123IRZA (Note) ISL6124IRZA (Note) ISL6125IRZA (Note) ISL6126IRZA (Note) ISL6127IRZA (Note) ISL6128IRZA (Note) ISL6130IRZA (Note) ISL612XSEQEVAL1 ISL6125EVAL1 *Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING ISL6123IR ISL6124IR ISL6125IR ISL6126IR ISL6127IR ISL6128IR 6123IRZ 6124IRZ 6125IRZ 6126IRZ 6127IRZ 6128IRZ 6130IRZ TEMP. RANGE (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) 24 Ld 4x4 QFN (Pb-free) PKG. DWG. # L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 L24.4x4 ISL612X Evaluation Platform ISL6125 Evaluation Platform AIN BIN CIN DIN AOUT BOUT COUT DOUT ISL6123 Block Diagram (1/4) VDD BIAS LOCK OUT VDD+5V Q-PUMP 1µA GATE D GATE C GATE B GATE A DIN CIN BIN AIN 1µA DLY_ONX VDD ENABLE SYSRST# RESET# GROUND DLY_OFF_A DLY_OFF_B DLY_OFF_C UVLO_A UVLO_B UVLO_C UVLO_D DLY_OFF_D 1.26V 1µA -1µA DLY_ON_A DLY_ON_B DLY_ON_C DLY_ON_D DLY_OFFX 10ms RISING DELAY 1.26V FIGURE 1. TYPICAL ISL6123 APPLICATION USAGE 30µs FILTER UVLOX LOGIC 0.633V EN SYSRST 150ms RISING DELAY GATEX RESET# 2 FN9005.8 February 5, 2007 ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 Pin Descriptions PIN # 23 10 1 11 24 9 PIN NAME VDD GND FUNCTION Chip Bias Bias Return Bias IC from nominal 1.5V to 5V IC ground Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is disabled for 10ms after UVLO is satisfied. ISL6123 and ISL6130 have ENABLE. ISL6124, ISL6125, ISL6126 and ISL6127 have ENABLE#. Only ISL6128 has 2 ENABLE# inputs, 1 for each 2 channel grouping. EN_1# for (A, B), and EN_2# for (C, D). RESET# provides a low signal 150ms after all GATEs are fully enhanced. This delay is for stabilization of output voltages. RESET# will assert low upon UVLO not being satisfied or ENABLE/ENABLE# being deasserted. The RESET outputs are open drain N channel FET and is guaranteed to be in the correct state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X. RESET#_2 only exists on ISL6128 for (C, D) group I/O. These inputs provide for a programmable UV lockout referenced to an internal 0.633V reference and are filtered to ignore short (<30µs) transients below programmed UVLO level. DESCRIPTION ENABLE_1/ Input to start on/off ENABLE#_1 sequencing. ENABLE#_2 RESET# RESET#_2 RESET# Output 20 12 17 14 21 8 16 15 18 13 3 4 2 5 6 7 22 UVLO_A UVLO_B UVLO_C UVLO_D DLY_ON_A DLY_ON_B DLY_ON_C DLY_ON_D Under Voltage Lock Out/Monitoring Input Gate On Delay Timer Output Allows for programming the delay and sequence for Vout turn-on using a capacitor to ground. Each cap is charged with 1µA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current source providing delay to the associated FETs GATE turn-on. These pins are NC on ISL6126, ISL6127 and ISL6130. DLY_OFF_A Gate Off Delay Timer Output DLY_OFF_B DLY_OFF_C DLY_OFF_D GATE_A GATE_B GATE_C GATE_D SYSRST# System Reset I/O FET Gate Drive Output ISL6125 Open Drain Outputs Allows for programming the delay and sequence for Vout turn-off through ENABLE/ENABLE# via a capacitor to ground. Each cap is charged with a 1µA internal current source to an internal reference voltage causing the corresponding gate to be pulled down turning-off the FET. These pins are NC on ISL6127. Drives the external FETs with a 1µA current source to soft start ramp into the load. On the ISL6125 only, these are open drain outputs that can be pulled up to a maximum of VDD voltage. As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low. This input can also be used to initiate the programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from input signal on this pin being driven high to first GATE. As an output when there is a UV condition, this pin pulls low. If common to other SYSRST# pins in a multiple IC configuration, it will cause immediate and unconditional latch-off of all other GATEs on all other ISL612X sequencers. This pin is a NC on ISL6126 and ISL6128 and ISL6130. No Connect 19 No Connect No Connect 3 FN9005.8 February 5, 2007 ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 ISL612X Variant Feature Matrix NUMBER OF NUMBER OF CHANNELS THAT UVLO TURN-OFF INPUTS GATE DRIVE REQUIRED WHEN 1 OR OPEN CONDITIONS MONITORED UVLO BY EACH FOR INITIAL DRAIN CMOS/ FAULTS RESET# START-UP OUTPUTS TTL TTL Gate Drive 4 UVLO 1 EN 4 UVLO 1 EN 4 UVLO 1 EN 1 UVLO 1 EN 4 UVLO 4 Gates PART NAME ISL6123 EN/EN# EN PRESET OR ADJUSTABLE SEQUENCE NUMBER OF UVLO AND PAIRS OF I/O FEATURES Time Adjustable 4 Monitors with Auto Restart, On and Off 1 I/O Low bias current sleep Time Adjustable 4 Monitors with Auto Restart On and Off 1 I/O ISL6124 ISL6125 EN# EN# CMOS CMO Gate Drive Open Drain 4 UVLO 4 UVLO 4 Gates 4 Open Drain Time Adjustable 4 Monitors with Auto Restart, Open On and Off 1 I/O Drain Sequenced Outputs 1 Gate 4 Mon