In-System Programmable E2CMOS PLD

Specifications ispGAL22V10 ispGAL22V10 In-System Programmable E2CMOS PLD Generic Array Logic™ FEATURES • IN-SYSTEM PROGRAMMABLE™ (5-V ONLY) — 4-Wire Serial Programming Interface — Minimum 10,000 Program/Erase Cycles — Built-in Pull-Down on SDI Pin Eliminates Discrete Resistor on Board (ispGAL22V10C Only) • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 111 MHz — 5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS • COMPATIBLE WITH STANDARD 22V10 DEVICES — Fully Function/Fuse-Map/Parametric Compatible with Bipolar and CMOS 22V10 Devices • E2 CELL TECHNOLOGY — In-System Programmable Logic — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention • TEN OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs • APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Software-Driven Hardware Configuration • ELECTRONIC SIGNATURE FOR IDENTIFICATION DESCRIPTION PIN CONFIGURATION The ispGAL22V10, at 7.5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the industry's first in-system programmable 22V10 device. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The ispGAL22V10 is fully function/fuse map/parametric compatible with standard bipolar and CMOS 22V10 devices. The standard PLCC package provides the same functional pinout as the standard 22V10 PLCC package with No-Connect pins being used for the ISP interface signals. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified. I I I MODE I I I 11 12 14 16 18 19 7 5 www.DataSheet4U.com FUNCTIONAL BLOCK DIAGRAM RESET I/CLK 8 OLMC I/O/Q I 10 I 12 OLMC I/O/Q I OLMC I/O/Q PROGRAMMABLE AND-ARRAY (132X44) I 14 OLMC I/O/Q I 16 OLMC I/O/Q I 16 OLMC I/O/Q I 14 OLMC I I/O/Q 12 I OLMC I/O/Q I 10 OLMC I/O/Q I SDO SDI MODE SCLK PROGRAMMING LOGIC 8 OLMC I/O/Q PRESET PLCC I/CLK SCLK I/O/Q I/O/Q I I Vcc SSOP 4 2 28 26 25 I/O/Q I/O/Q SCLK I/CLK I I I I I MODE I I I I I GND 1 28 Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q SDO I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I SDI ispGAL22V10 Top View 23 I/O/Q SDO 7 ispGAL 22V10 22 Top View 9 21 I/O/Q I/O/Q I/O/Q 14 15 I I GND SDI I Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. I/O/Q I/O/Q LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com July 1997 isp22v10_02 1 Specifications ispGAL22V10 ORDERING INFORMATION Commercial Grade Specifications Tpd (ns) 7.5 Tsu (ns) 6.5 Tco (ns) 5 Icc (mA) 140 Ordering # ispGAL22V10C-7LJ ispGAL22V10C-7LK ispGAL22V10B-7LJ 10 7 7 140 ispGAL22V10C-10LJ ispGAL22V10C-10LK ispGAL22V10B-10LJ 15 10 8 140 ispGAL22V10C-15LJ ispGAL22V10C-15LK ispGAL22V10B-15LJ Package 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC Industrial Grade Specifications Tpd (ns) 15 Tsu (ns) 10 Tco (ns) 8 Icc (mA) 165 Ordering # ispGAL22V10C-15LJI ispGAL22V10C-15LKI Package 28-Lead PLCC 28-Lead SSOP PART NUMBER DESCRIPTION XXXXXXXX _ XX X X X ispGAL22V10C Device Name ispGAL22V10B Speed (ns) L = Low Power Power Grade Blank = Commercial I = Industrial Package J = PLCC K = SSOP 2 Specifications ispGAL22V10 OUTPUT LOGIC MACROCELL (OLMC) The ispGAL22V10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The ispGAL22V10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. A R D Q CLK SP Q 4 TO 1 MUX 2 TO 1 MUX ispGAL22V10 OUTPUT LOGIC MACROCELL (OLMC) OUTPUT LOGIC MACROCELL CONFIGURATIONS Each of the Macrocells of the ispGAL22V10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “productterm driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. 3 Specifications ispGAL22V10 REGISTERED MODE AR AR D Q D Q CLK SP Q CLK SP Q ACTIVE LOW S0 = 0 S1 = 0 S0 = 1 S1 = 0 ACTIVE HIGH COMBINATORIAL MODE ACTIVE LOW S0 = 0 S1 = 1 S0 = 1 S1 = 1 ACTIVE HIGH 4 Specifications ispGAL22V10 ispGAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP PLCC & SSOP Package Pinout 2 0 0000 0044 . . . 0396 4 8 12 16 20 24 28 32 36 40 ASYNCHRONOUS RESET (TO ALL REGISTERS) 8 OLMC S0 5808 S1 5809 27 0440 . . . . 0880 10 OLMC S0 5810 S1 5811 26 3 0924 . . . . . 1452 12 OLMC S0 5812 S1 5813 25 4 1496 . . . . . . 2112 14 OLMC S0 5814 S1 5815 24 5 2156 . . . . . . . 2860 16 OLMC S0 5816 S1 5817 23 6 2904 . . . . . . . 3608 16 OLMC S0 5818 S1 5819 21 7 3652 . . . . . . 4268 14 OLMC S0 5820 S1 5821 20 9 4312 . . . . . 4840 12 OLMC S0 5822 S1 5823 19 10 4884 . . . . 5324 10 OLMC S0 5824 S1 5825 18 11 5368 . . . 5720 8 OLMC S0 5826 S1 5827 17 12 5764 13 5828, 5829 ... M S B L S B SYNCHRONOUS PRESET (TO ALL REGISTERS) 16 Electronic Signature ... 5890, 5891 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 5 Specifications ispGAL22V10C Specifications ispGAL22V10 ispGAL22V10B ABSOLUTE MAXIMUM RATINGS(1) Supply voltage VCC ....................................... -0.5 to +7V Input voltage applied ........................... -2.5 to VCC +1.0V Off-state output voltage applied........... -2.5 to VCC +1.0V Storage Temperature.................................. -65 to 150°C Ambient Temperature with Power Applied ......................................... -55 to 125°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). RECOMMENDED OPERATING COND. Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75°C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (TA) ............................ -40 to 85°C Supply voltage (VCC) with Respect to Ground ..................... +4.50 to +5.50V DC ELECTRICAL CHARACTERISTICS Over Recommended Operating Conditions (Unless Otherwise Specified) S