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ISD5216
8 TO 16 MINUTES VOICE RECORD/PLAYBACK DEVICE WITH INTEGRATED CODEC
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Publication Release Date: June, 2003 Revision B.2
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ISD5216
1. GENERAL DESCRIPTION
The ChipCorder ISD5216 is an 8 to 16 minute Voice and Data Record and Playback system with integrated Voice band CODEC. The device works on a single 2.7V to 3.3V supply, and has fully integrated system functions, including: AGC, microphone preamplifier, speaker driver, memory and CODEC. The CODEC meets the PCM conformance specification of the G.714 recommendation. Its µLaw and A-Law compander meets the specification of the ITU-T G.711 recommendation.
2. FEATURES
• • • • • • • • • • •
Single Supply 2.7 to 3.3 Volt operation Voice and digital data record and playback system on a single chip Industry-leading sound quality Low voltage operation Message management Fully integrated system functions Flexible architecture Nonvolatile message storage Configurable ChipCorder sampling rates of 4 kHz, 5.3kHz, 6.4 kHz and 8kHz 8, 10, 12 and 16 minutes duration External or internal Voice recorder clock serial interface (400kHz) Configurable analog paths 2.2V Microphone Bias Pin 100 year message retention (typical) 100K analog record cycles (typical) 10K digital record cycles (typical) Full-duplex (not in I2S mode) single channel speech CODEC with: o External 13.824 MHz, 27.648 MHz, 20.48 MHz or 40.96 MHz master clock 2S and PCM digital audio interface ports oI o Serial transfer data rate from 64 to 3072 Kbps o Short and Long frame sync formats o 2s complement and signed magnitude data format o Complete µ-Law and A-Law companding o Linear 14 bit ∆Σ PCM CODEC-filter for A/D and D/A converter o 8 kHz or 44.1 kHz – 48 kHz digital audio sampling rate options o Analog receive and transmit gain adjust o Configurable setup through the I2C interface
• I2C • • • • • •
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ISD5216
3. BLOCK DIAGRAM
I5216 Block Diagram
MICBS
MICROPHONE 2.2V Voltage reference
(AGPD)
1
MIC+ MIC AGCCAP
MIC IN
INP SUM1 MUX
AGC
(AGPD) AUX IN
1
Σ
2
SUM1 Summing AMP SUM1 ARRAY
SUM1
Input Source MUX
Auto mute Auto gain
1
Low Pass Filter
1
FILTO AUX IN
2
( S1M0 ) S1M1
FILTO
Σ
SUM2 Summing AMP
Filter MUX
1 (FLS0)
(AMT0)
(FLPD)
( S2M0) S2M1
1.0 / 1.4 / 2.0 / 2.8
SUM1 MUX
AUX IN
AUX IN AMP
(INS0) (AXPD)
1
1
ARRAY
Internal Clock
DAO
2
( AXG0) AXG1
÷2
1 (CKD2)
( OSPD) 2 ( FLD0 ) CKDV FLD1
SUM2
(ANALOG)
Multilevel Storage Array
2
2
MCLK
MIC+ MIC-
( S1S0 ) S1S1
ARRAY OUT
(ANALOG)
2 x 64 S/H
Array I/O Mux Program/Read Control
FILTO
AUX OUT AMP
AUX OUT
Output MUX
CTRL
(DIGITAL)
A/D
2 x 64-bit reg.
SUM2 VOL
ARRAY OUT
(DIGITAL)
SPEAKER
Spkr. AMP
INP
SUM2
SUM1 INP DAO SUM2
DAO
2
SP+ SP-
( )
CDI0 CDI1
CODEC Mux
2
Volume Control
1 (VLPD)
3
( )
VOL0 VOL1 VOL2
( OPS0 ) OPS1
(
OPA0 OPA1
2
)
Vol MUX
2
µ-Law / A-Law / Linear 14 bit CODEC
( VLS0 ) VLS1
(ADPD) DAPD
2
Power Conditioning
PCM / I2S Interface
Device Control
VCCA
VSSA
VSSA
VSSD
VSSD
VCCD
VCCD
WS
SCK
SDIO
SDI
SCL
SDA
INT
RAC
A0
A1
5/22/01
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Publication Release Date: June, 2003 Revision B.2
www.DataSheet4U.com
ISD5216
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM .............................................................................................................................. 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 7 6. PIN DESCRIPTION ............................................................................................................................. 8 7. FUNCTIONAL DESCRIPTION............................................................................................................ 9 7.1. MEMORY ORGANIZATION ........................................................................................................ 11 7.2. CODEC ........................................................................................................................................ 11 7.2.1. Analog Input to Digital Output Path....................................................................................... 12 7.2.2. Digital Input to Analog Output Path....................................................................................... 13 7.2.3. CODEC External Clock Configuration .................................................................................. 13 7.2.4. ChipCorder Analog Array Sampling Frequency With External Clock ................................... 14 7.3. I2C INTERFACE........................................................................................................................... 15 7.3.1. System configuration............................................................................................................. 15 7.3.2. Start and stop conditions ...................................................................................................... 15 7.3.3. Bit transfer ............................................................................................................................. 16 7.3.4. ACKNOWLEDGE.................................................................................................................. 16 7.3.5. Additional ISD5216 flow control ............................................................................................ 17 7.3.6. I2C Protocol Addressing ........................................................................................................ 17 7.3.7. I2C Slave Address ................................................................................................................. 19 7.4. I2S SERIAL INTERFACE ............................................................................................................ 20 7.4.1. Serial Data ............................................................................................................................ 20 7.4.2. Word Select........................................................................................................................... 21 7.4.3. Timing.................................................................................................................................... 21 7.5. CONTROL REGISTERS ............................................................................................................. 22 7.5.1. Command Byte ..................................................................................................................... 22 7.5.2. Function Bits ......................................................................................................................... 23 7.5.3. Register Bits.......................................................................................................................... 23 7.5.4. OPCODE Command Byte Table........................................................................................... 24 7.5.5. Power-up ............................................................................................................................... 25 7.5.6. Read Status .......................................................................................................................... 25 7.5.7. Attaching an Address to a Command ................................................................................... 25 7.5.8. Playback Mode...................................................................................................................... 26 7.5.9. Record Mode......................................................................................................................... 26 -4-
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ISD5216
7.5.10. Message Cueing ................................................................................................................. 26 7.6. digital mode.................................................................................................................................. 26 7.6.1. Writing Data .......................................................................................................................... 26 7.6.2. Reading Data ........................................................................................................................ 26 7.6.3. Erasing Data ......................................................................................................................... 27 7.6.4. Load Configuration Registers ............................................................................................... 27 7.7. ISD5216 ANALOG STRUCTURE (Left Half) description ............................................................ 31 7.7.1 Speaker, AUX OUT and Volume Control Description ........................................................... 33 7.7.2. Microphone and Auxiliary Inputs........................................................................................... 34 7.7.3. CODEC Configuration (First Page)....................................................................................... 35 7.8. PIN DETAILS ............................................................................................................................... 36 7.8.1. Power and Ground Pins ........................................................................................................ 37 7.8.2. Digital I/O Pins: ..................................................................................................................... 37 7.8.3. CODEC Iinterface Pincs ...
