(IRS2184 / IRS21844) HALF-BRIDGE DRIVER

www.DataSheet4U.com Data Sheet No. PD60252 IRS2184/IRS21844(S)PbF Features • • • • • • • • • • • Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for both channels 3.3 V and 5 V input logic compatible Matched propagation delay for both channels Logic and power ground +/- 5 V offset Lower di/dt gate driver for better noise immunity Output source/sink current capability 1.4 A/1.8 A RoHS compliant Packages HALF-BRIDGE DRIVER 8-Lead PDIP IRS2184 14-Lead PDIP IRS21844 8-Lead SOIC IRS2184S 14-Lead SOIC IRS21844S Description The IRS2184/IRS21844 are high voltage, high speed power MOSFET and Feature Comparison CrossIGBT drivers with dependent high-side ton/toff Deadtime Input conduction Ground Pins Part and low-side referenced output chanlogic prevention (ns) (ns) logic nels. Proprietary HVIC and latch 2181 COM HIN/LIN no none 180/220 immune CMOS technologies enable 21814 VSS/COM ruggedized monolithic construction. 2183 Internal 400 COM HIN/LIN yes 180/220 21834 Program 400-5000 VSS/COM The logic input is compatible with stan2184 Internal 400 COM IN/SD yes 680/270 dard CMOS or LSTTL output, down to 3.3 21844 Program 400-5000 VSS/COM V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V. Typical Connection VCC up to 600 V VCC IN SD VB HO VS LO up to 600 V TO LOAD IN SD COM IRS2184 VCC IN SD VCC IN SD DT VSS RDT VSS HO VB VS IRS21844 TO LOAD (Refer to Lead Assignments for correct configuration).These diagrams show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. COM LO www.irf.com 1 IRS2184/IRS21844(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO DT VIN VSS dVS/dt Definition High-side floating absolute voltage High-side floating supply offset voltage High-side floating output voltage Low-side and logic fixed supply voltage Low-side output voltage Programmable deadtime pin voltage (IRS21844 only) Logic input voltage (IN & SD) Logic ground (IRS21844 only) Allowable offset supply voltage transient (8-lead PDIP) (8-lead SOIC) (14-lead PDIP) (14-lead SOIC) (8-lead PDIP) (8-lead SOIC) (14-lead PDIP) (14-lead SOIC) Min. -0.3 VB - 20 VS - 0.3 -0.3 -0.3 VSS - 0.3 VSS - 0.3 VCC - 20 — — — — — — — — — — -50 — Max. 620 (Note 1) VB + 0.3 VB + 0.3 20 (Note 1) VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 50 1.0 0.625 1.6 1.0 125 200 75 120 150 150 300 Units V V/ns PD Package power dissipation @ TA ≤ +25 °C W RthJA Thermal resistance, junction to ambient °C/W TJ TS TL Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) °C Note 1: All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply. Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset rating are tested with all supplies biased at a 15 V differential. Symbol VB VS VHO VCC VLO VIN DT VSS TA Definition High-side floating supply absolute voltage High-side floating supply offset voltage High-side floating output voltage Low-side and logic fixed supply voltage Low-side output voltage Logic input voltage (IN & SD) Programmable deadtime pin voltage (IRS21844 only) Logic ground (IRS21844 only) Ambient temperature Min. VS + 10 Note 2 VS 10 0 VSS VSS -5 -40 Max. VS + 20 600 VB 20 VCC VCC VCC 5 125 Units V °C Note 2: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip DT97-3 for more details). www.irf.com 2 IRS2184/IRS21844(S)PbF Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15 V, VSS = COM, CL = 1000 pF, TA = 25° C, DT = VSS unless otherwise specified. Symbol ton toff tsd MTon MToff tr tf DT MDT Definition Turn-on propagation delay Turn-off propagation delay Shut-down propagation delay Delay matching, HS & LS turn-on Delay matching, HS & LS turn-off Turn-on rise time Turn-off fall time Deadtime: LO turn-off to HO turn-on(DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime matching = DTLO - HO - DTHO-LO Min. — — — — — — — 280 4 — — Typ. 680 270 180 0 0 40 20 400 5 0 0 Max. Units Test Conditions 900 400 270 90 40 60 35 520 6 50 600 µs ns VS = 0 V RDT= 0 Ω RDT = 200 kΩ RDT=0 Ω RDT = 200 kΩ ns VS = 0 V VS = 0 V or 600 V Static Electrical Characteristics VBIAS (VCC, VBS ) = 15 V, VSS = COM, DT= VSS and TA = 25 °C unless otherwise specified. The VIL, VIH, and IIN parameters are referenced to VSS /COM and are applicable to the respective input leads: IN and SD. The VO, IO, and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol VIH VIL VSD,TH+ VSD,THVOH VOL ILK IQBS IQCC IIN+ IINVCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH IO+ IO- Definition Logic “1” input voltage for HO & logic “0” for LO Logic “0” input voltage for HO & logic “1” for LO SD input positive going threshold SD input negative going threshold High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic “1” input bias current Logic “0” input bias current VCC and VBS supply undervoltage positive going threshold VCC and VBS supply undervoltage negative going threshold Hysteresis Output high short circuit pulsed current Output low short circuit pulsed current Min. Typ. Max. Units Test Conditions 2.5 — 2.5 — — — — 20 0.4 — — 8.0 7.4 0.3 1.4 1.8 — — — — — — — 60 1.0 25 — 8.9 8.2 0.7 1.9 2.3 — 0.8 — 0.8 1.4 0.2 50 150 1.6 60 5.0 9.8 9.0 V — — A — VO = 0 V, PW ≤ 10 µs VO = 15 V, PW ≤ 10 µs µA mA µA V IO = 0 A IO = 20 mA VB = VS = 600 V VIN = 0 V or 5 V IN = 5 V, SD = 0 V IN = 0 V, SD = 5 V VCC = 10 V to 20 V www.irf.com 3 IRS2184/IRS21844(S)PbF Functional Block Diagrams VB 2184 IN VSS/COM LEVEL SHIFT HV LEVEL SHIFTER PULSE GENERATOR UV DETECT R PULSE FILTER R S Q HO VS DEADTIME UV DETECT VCC +5V LO SD VSS/COM LEVEL SHIFT DELAY COM VB 21844 IN VSS/COM LEVEL SHIFT HV LEVEL SHIFTER PULSE GENERATOR UV DETECT R PULSE FILTER R S Q HO VS DT +5V DEADTIME UV DETECT VCC LO SD VSS/COM LEVEL SHIFT DELAY COM VSS www.irf.com 4 IRS2184/IRS21844(S)PbF Lead Definitions Symbol Description IN SD DT VSS VB HO VS VCC LO COM Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO (referenced to COM for IRS2184 and VSS for IRS21844) Logic input for shutdown (referenced to COM for IRS2184 and VSS for IRS21844) Programmable deadtime lead, referenced to VSS. (IRS21844 only) Logic ground (IRS21844 only) High-side floating supply High-side gate drive output High-side floating supply return Low-side and logic fixed supply Low-side gate drive output Low-side return Lead Assignments 1 2 3 4 IN SD COM LO VB HO VS VCC 8 7 6 5 1 2 3 4 IN SD COM LO VB HO VS VCC 8 7 6 5 8-Lead PDIP 8-Lead SOIC IRS2184PbF 1 2 3 4 5 6 7 IN SD VSS DT COM LO VCC VB HO VS IRS2184SPbF 14 13 12 11 10 9 8 1 2 3 4 5 6 7 IN SD VSS DT COM LO VCC VB HO VS 14 13 12 11 10 9 8 14-Lead PDIP 14-Lead SOIC IRS21844PbF www.irf.com IRS21844SPbF 5 IRS2184/IRS21844(S)PbF IN IN(LO) 50% 50% SD IN(HO) ton tr 90% toff 90% tf HO LO LO HO Figure 1. Input/Output Timing Diagram 10% 10% Figure 2. Switching Time Waveform Definitions 50% 50% IN 90% SD 50% HO LO tsd DT LO-HO 10% DTHO-LO 90% HO LO 90% MDT= DTLO-HO 10% - DTHO-LO Figure 3. Shutdown Waveform Definitions Figure 4. Deadtime Waveform Definitions IN(LO) 50% 50% IN (HO) LO HO 10% MT 90% MT LO HO Figure 5. Delay Matching Waveform Definitions www.irf.com 6 IRS2184/IRS21844(S)PbF Turn-on Propagation Delay (ns) Turn-on Propagation Delay (ns) 1400 1200 1000 Max. 1400 1200 1000 800 600 400 10 12 14 16 18 20 Supply Voltage (V) Figure 6B. Turn-On Propagation Delay vs. Supply Voltage Max. 800 Typ. Typ. 600 400 -50 -25 0 25 50 75 100 125 Temperature (oC) Figure 6A. Turn-On Propagation Delay vs. Tem perature T u rn -o f f P ro p a g a t i o n D e l a y (n s ) 600 500 400 Max. Turn-off Propagation Delay (ns) 700 700 600 500 Max. 400 Typ. 300 Typ. 300 200 100 10 12 14 16 18 20 200 100 -50 -25 0 25 50 75 100 125 Temperature (oC) Figure 7A. Turn-Off Propagation Delay vs. Tem perature Supply Voltage (V) Figure 7B. Turn-Off Propagation Delay vs. Supply Voltage www.irf.com 7 IRS2184/IRS21844(S)PbF 500 SD Propagation Delay (ns) SD Propagation Delay (ns) 500 400 300 Max. 400 Max. 300 Typ. 200 Typ. 200 100 0 -50 -25 0 25 50 o 100 0 75 100 125 10 12 14 16 18 20 Temperature ( C) Figure 8A. SD Propagation Delay vs. Tem perature Supply Voltage (V) Figure 8B. SD Propagation Delay vs. Supply Voltage 120 Turn-On Rise Time (ns) Turn-On Rise Time (ns) -25 0 25 50 75 100 125 100 80 60 40 20 0 -50 Temperature (oC) Figure 9A. Turn-On Rise Tim e vs. Tem perature Max Typ. 120 100 80 60 40 20 0 10 12 14 16 18 20 Max. Typ. Supply Voltage (V) Figure 9B. Turn-On Rise Tim e vs. Supply Voltage www.irf.com 8 IRS2184/IRS21844(S)PbF 80 Turn-Off Fall Time (ns) 80 60 40 Max. Turn-Off Fall Time (ns) 60 Max. 40 Typ. 20 0 -50 Typ 20 -25 0 25 50 o 75 100 125 0 10 12 14 16 18 20 Temperature ( C) Figure 10A. Turn-Off Fall Tim e vs. Tem perature Suppl