HEXFET Power MOSFET

PD - 94662 IRLR7807Z IRLU7807Z Applications High Frequency Synchronous Buck Converters for Computer Processor Power Benefits Very Low RDS(on) at 4.5V VGS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current HEXFET® Power MOSFET VDSS RDS(on) max Qg (typ.) 30V 13.8mΩ 7.0nC D-Pak IRLR7807Z I-Pak IRLU7807Z Absolute Maximum Ratings Parameter VDS VGS ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C PD @TC = 100°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case) Max. 30 ± 20 43 30 170 40 20 0.27 -55 to + 175 Units V A W W/°C °C Thermal Resistance Parameter RθJC RθJA RθJA Junction-to-Case Junction-to-Ambient (PCB Mount) Junction-to-Ambient Typ. ––– ––– ––– Max. 3.75 50 110 Units °C/W Notes through are on page 11 www.irf.com 1 4/7/03 IRLR/U7807Z Static @ TJ = 25°C (unless otherwise specified) Parameter BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units 30 ––– ––– ––– 1.35 ––– ––– ––– ––– ––– 51 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 23 11 14.5 1.8 -4.5 ––– ––– ––– ––– ––– 7.0 1.8 0.7 2.7 1.8 3.4 4.0 7.1 28 9.8 3.5 780 180 100 ––– ––– V Conditions VGS = 0V, ID = 250µA mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 15A 13.8 18.2 2.25 ––– 1.0 150 100 -100 ––– 11 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– pF VGS = 0V VDS = 15V ƒ = 1.0MHz ns nC VDS = 15V, VGS = 0V VDD = 15V, VGS = 4.5V ID = 12A Clamped Inductive Load nC VDS = 15V VGS = 4.5V ID = 12A See Fig. 16 S nA V mV/°C µA VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VDS = 15V, ID = 12A VGS = 4.5V, ID = 12A VDS = VGS, ID = 250µA Avalanche Characteristics EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Typ. ––– ––– ––– Max. 28 12 4.0 Units mJ A mJ Diode Characteristics Parameter IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units ––– ––– ––– ––– ––– ––– ––– ––– 23 14 43 A 170 1.0 35 21 V ns nC Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V TJ = 25°C, IF = 12A, VDD = 15V di/dt = 100A/µs Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com IRLR/U7807Z 1000 TOP VGS 1000 VGS ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 100 10 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V BOTTOM 2.25V 100 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V BOTTOM 2.25V TOP 1 10 0.1 2.5V 0.01 1 2.5V 20µs PULSE WIDTH Tj = 175°C 20µs PULSE WIDTH Tj = 25°C 0.001 0.1 1 10 0.1 0.1 1 10 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000.0 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID = 30A VGS = 10V ID, Drain-to-Source Current (Α) T J = 25°C T J = 175°C 100.0 1.5 10.0 1.0 1.0 VDS = 10V 20µs PULSE WIDTH 0.1 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3 IRLR/U7807Z 10000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds C rss = C gd C oss = C ds + C gd SHORTED 12 ID= 12A VGS, Gate-to-Source Voltage (V) 10 VDS= 24V VDS= 15V C, Capacitance (pF) 1000 Ciss 8 Coss 100 6 Crss 4 2 10 1 10 100 0 0 4 8 12 16 VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000.0 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) ISD, Reverse Drain Current (A) 100.0 T J = 175°C 10.0 ID, Drain-to-Source Current (A) 100 10 100µsec 1.0 T J = 25°C VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-toDrain Voltage (V) 1 Tc = 25°C Tj = 175°C Single Pulse 0.1 0.1 1.0 10.0 1msec 10msec 100.0 1000.0 VDS , Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U7807Z 50 LIMITED BY PACKAGE 40 ID , Drain Current (A) 2.5 VGS(th) Gate threshold Voltage (V) 2.0 30 ID = 250µA 20 1.5 10 0 25 50 75 100 125 150 175 T C , Case Temperature (°C) 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature 10 Thermal Response ( Z thJC ) D = 0.50 1 0.20 0.10 0.05 R1 R1 τJ τ1 τ2 R2 R2 R3 R3 τ3 τC τ τ3 0.1 0.02 0.01 τJ Ri (°C/W) τi (sec) 1.796 0.000267 1.112 0.842 0.000607 0.004249 τ1 τ2 0.01 SINGLE PULSE ( THERMAL RESPONSE ) Ci= τi/Ri Ci τi/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1 0.001 1E-006 1E-005 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U7807Z 15V 120 EAS, Single Pulse Avalanche Energy (mJ) TOP VDS L DRIVER 100 BOTTOM ID 3.0A 1.4A 12A RG VGS 20V D.U.T IAS tp + V - DD 80 A 0.01Ω 60 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 40 20 0 25 50 75 100 125 150 175 Starting T J, Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS LD VDS VDS 90% + VDD - Fig 12b. Unclamped Inductive Waveforms 10% D.U.T Current Regulator Same Type as D.U.T. VGS VGS Pulse Width < 1µs Duty Factor < 0.1% td(on) 50KΩ 12V .2µF .3µF Fig 14a. Switching Time Test Circuit D.U.T. + V - DS VGS 3mA IG ID Current Sampling Resistors Fig 13. Gate Charge Test Circuit Fig 14b. Switching Time Waveforms 6 www.irf.com IRLR/U7807Z Driver Gate Drive D.U.T + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer Reverse Recovery Current P.W. Period D= P.W. Period VGS=10V * + D.U.T. ISD Waveform Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt - - + VDD RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRLR/U7807Z Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by; * P =P loss conduction + P drive + P output P = Irms × Rds(on) loss + (Qg × Vg × f ) ( 2 ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput This can be expanded and approximated by; Q  +  oss × Vin × f + (Qrr × Vin × f )  2 *dissipated primarily in Q1. Ploss = (Irms × Rds(on ) ) 2   Qgs2 Qgd +I× × Vin × f  +  I × × Vin × ig ig   + (Qg × Vg × f ) +  Qoss × Vin × f  2   f  This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on an