PD - 96045
Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l Lead-Free Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current
IRFR3707ZCPbF IRFU3707ZCPbF
HEXFET® Power MOSFET
VDSS RDS(on) max
30V 9.5m:
Qg
9.6nC
D-Pak IRFR3707ZCPbF
I-Pak IRFU3707ZCPbF
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C PD @TC = 100°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
Max.
30 ± 20 56 39
Units
V A
f f
220 50 25 0.33 -55 to + 175 300 (1.6mm from case) W/°C °C W
Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Thermal Resistance
Parameter
RθJC RθJA RθJA Junction-to-Case Junction-to-Ambient (PCB Mount) Junction-to-Ambient
Typ.
Max.
3.0 50 110
Units
°C/W
gÃ
––– ––– –––
Notes through are on page 11
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1
06/22/06
IRFR/U3707ZCPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
30 ––– ––– ––– 1.35 ––– ––– ––– ––– ––– 71 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 0.023 7.5 10 1.80 -5.0 ––– ––– ––– ––– ––– 9.6 2.6 0.90 3.5 2.6 4.4 5.8 8.0 11 12 3.3 1150 260 120 ––– ––– 9.5 12.5 2.25 ––– 1.0 150 100 -100 ––– 14 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– pF VGS = 0V VDS = 15V ns nC nC VDS = 15V VGS = 4.5V ID = 12A S nA V mV/°C µA V
Conditions
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 15A VGS = 4.5V, ID = 12A
e e
VDS = VGS, ID = 250µA VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VDS = 15V, ID = 12A
See Fig. 16 VDS = 15V, VGS = 0V VDD = 16V, VGS = 4.5V ID = 12A Clamped Inductive Load
e
ƒ = 1.0MHz
Avalanche Characteristics
EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current
Ã
d
Typ. ––– ––– –––
Max. 42 12 5.0
Units mJ A mJ
Repetitive Avalanche Energy
––– ––– ––– ––– ––– ––– ––– ––– 25 17
Diode Characteristics
Parameter
IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)
Min. Typ. Max. Units
56
f
Conditions
MOSFET symbol
D
A 220 1.0 38 26 V ns nC
Ã
showing the integral reverse
G S
Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V TJ = 25°C, IF = 12A, VDD = 15V di/dt = 100A/µs
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFR/U3707ZCPbF
10000
TOP
1000
VGS 10V 6.0V 4.5V 4.0V 3.3V 2.8V 2.5V 2.2V
TOP VGS 10V 6.0V 4.5V 4.0V 3.3V 2.8V 2.5V 2.2V
1000
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
BOTTOM
100
BOTTOM
10 1 0.1
10
2.2V
1
2.2V
0.01 0.001 0.1 1 10
20µs PULSE WIDTH Tj = 25°C
0.1 0.1
20µs PULSE WIDTH Tj = 175°C
1 10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current (Α)
100
ID = 30A VGS = 10V
T J = 175°C
1.5
10
1
1.0
0.1
TJ = 25°C VDS = 10V 20µs PULSE WIDTH
0.01 0 2 4 6 8
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
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IRFR/U3707ZCPbF
10000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
6.0 ID= 12A
VGS, Gate-to-Source Voltage (V)
5.0
VDS= 24V VDS= 15V
C, Capacitance(pF)
4.0
1000
Ciss
3.0
Coss
2.0
1.0
Crss
100 1 10 100
0.0 0 2 4 6 8 10 12
VDS, Drain-to-Source Voltage (V)
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
1000.00
1000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100.00 T J = 175°C 10.00
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
10
100µsec 1msec
1.00
TJ = 25°C
1 Tc = 25°C Tj = 175°C Single Pulse 0.1 0 1 10 10msec
VGS = 0V 0.10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 VSD, Source-to-Drain Voltage (V)
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFR/U3707ZCPbF
60 50
ID, Drain Current (A)
2.5
Limited By Package
VGS(th) Gate threshold Voltage (V)
40 30
2.0
ID = 250µA
1.5
20
10
0 25 50 75 100 125 150 175 T C , Case Temperature (°C)
1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10. Threshold Voltage vs. Temperature
10
Thermal Response ( Z thJC )
D = 0.50
1
0.20 0.10 0.05
0.1
R1 R1 τJ τ1 τ2 R2 R2 R3 R3 τ3 τC τ τ3
0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE )
τJ
Ri (°C/W) τi (sec) 0.823 0.000128 1.698 0.481 0.000845 0.016503
τ1
τ2
0.01
Ci= τi/Ri Ci= τi/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFR/U3707ZCPbF
15V
200
EAS , Single Pulse Avalanche Energy (mJ)
180 160 140 120 100 80 60 40 20 0 25 50 75 100
VDS
L
DRIVER
ID TOP 3.7A 5.6A BOTTOM 12A
RG
20V VGS
D.U.T
IAS tp
+ V - DD
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy vs. Drain Current
I AS
LD VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1µs Duty Factor < 0.1%
50KΩ 12V .2µF .3µF
Current Regulator Same Type as D.U.T.
Fig 14a. Switching Time Test Circuit
D.U.T. + V - DS
VDS
90%
VGS
3mA
10%
IG ID
Current Sampling Resistors
VGS
td(on) tr td(off) tf
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRFR/U3707ZCPbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
• • • • dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
V DD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
Id Vds Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRFR/U3707ZCPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by;
* Ploss = Pconduction + P + Poutput drive
Ploss = Irms × Rds(on)
+ ( g × Vg × f ) Q
(
2
)
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝ 2 ⎠
*dissipated primarily in Q1.
Ploss = (Irms 2 × Rds(on ) ) ⎛ Qgd +⎜I × × Vin × ig ⎝ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠ ⎞ ⎞ ⎛ Qgs 2 f⎟ + ⎜ I × × Vin × f ⎟ ig ⎠ ⎝ ⎠
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied b
