HEXFET Power MOSFET

PD - 94444 SMPS MOSFET IRFIB8N50K HEXFET® Power MOSFET Applications l Switch Mode Power Supply (SMPS) l UninterruptIble Power Supply l High Speed Power Switching Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current VDSS 500V RDS(on) typ. 290mΩ ID 6.7A TO-220 FULL-PAK Absolute Maximum Ratings Parameter ID @ TC = 25°C Continuous Drain Current, VGS @ 10V ID @ TC = 100°C Continuous Drain Current, VGS @ 10V Pulsed Drain Current IDM Max. 6.7 4.2 27 45 0.36 ±30 17 -55 to + 150 Units A W W/°C V V/ns °C c PD @TC = 25°C VGS dv/dt TJ TSTG Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torqe, 6-32 or M3 screw e 300 (1.6mm from case ) 1.1(10) N•m (lbf•in) Avalanche Characteristics EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current c d Typ. ––– ––– ––– Max. 290 6.7 4.5 Units mJ A mJ Repetitive Avalanche Energy c Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient Typ. ––– ––– Max. 2.76 65 Units °C/W www.irf.com 1 4/21/04 IRFIB8N50K Static @ TJ = 25°C (unless otherwise specified) Parameter V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS IGSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. Typ. Max. Units 500 ––– ––– 3.0 ––– ––– ––– ––– ––– 0.59 290 ––– ––– ––– ––– ––– ––– ––– 350 5.0 50 250 100 -100 nA V Conditions VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 4.0A f V µA VDS = VGS, ID = 250µA VDS = 500V, VGS = 0V VDS = 400V, VGS = 0V, TJ = 125°C VGS = 30V VGS = -30V Dynamic @ TJ = 25°C (unless otherwise specified) Parameter gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. Typ. Max. Units 4.7 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 17 16 28 8.4 2160 240 27 2600 62 120 ––– 89 24 44 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– pF ns nC V ID = 6.7A VDS = 400V VGS = 10V ID = 6.7A RG = 38Ω VGS = 10V VGS = 0V VDS = 25V Conditions VDS = 50V, ID = 4.0A f f VDD = 250V ƒ = 1.0MHz VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz VGS = 0V, VDS = 400V, ƒ = 1.0MHz VGS = 0V, VDS = 0V to 400V e Diode Characteristics Parameter IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Min. Typ. Max. Units ––– ––– ––– ––– ––– ––– ––– ––– 430 2840 6.7 A 27 2.0 640 4270 V ns nC Conditions MOSFET symbol showing the integral reverse G D Ãch Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time S p-n junction diode. TJ = 25°C, IS = 6.7A, VGS = 0V f TJ = 25°C, IF = 6.7A di/dt = 100A/µs f Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes:  Repetitive rating; pulse width limited by max. junction temperature. (See Fig. 11). ‚ Starting TJ = 25°C, L = 13mH, RG = 25Ω, IAS = 6.7A, dv/dt = 17V/ns (See Figure 12a). ƒ ISD ≤ 6.7A, di/dt ≤ 330A/µs, VDD ≤ V(BR)DSS, TJ ≤ 150°C. „ Pulse width ≤ 300µs; duty cycle ≤ 2%. … Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . 2 www.irf.com IRFIB8N50K 1000 TOP VGS 15V 12V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 100 TOP VGS 15V 12V 10V 8.0V 7.0V 6.0V 5.5V 5.0V ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 100 10 BOTTOM 10 BOTTOM 1 1 5.0V 0.1 5.0V 0.01 0.1 20µs PULSE WIDTH Tj = 25°C 0.001 0.1 1 10 100 0.01 0.1 1 20µs PULSE WIDTH Tj = 150°C 10 100 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100.00 3.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID = 6.7A ID, Drain-to-Source Current (Α) 10.00 T J = 150°C 2.5 2.0 1.00 1.5 0.10 T J = 25°C VDS = 50V 20µs PULSE WIDTH 1.0 0.5 0.01 4.0 5.0 6.0 7.0 8.0 9.0 10.0 0.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( °C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRFIB8N50K 100000 VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd 12 ID = 6.7A 10 8 VGE (V) 10000 400V 250V 100V C, Capacitance(pF) Ciss 1000 6 4 100 Coss Crss 10 2 0 1 10 100 1000 1 0 10 20 30 40 50 60 70 VDS, Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100.00 100 OPERATION IN THIS AREA LIMITED BY R DS(on) ISD, Reverse Drain Current (A) 10.00 T J = 150°C ID, Drain-to-Source Current (A) 10 100µsec 1.00 TJ = 25°C 1msec 1 Tc = 25°C Tj = 150°C Single Pulse 0.1 1 10 100 10msec VGS = 0V 0.10 0.0 0.5 1.0 1.5 VSD, Source-toDrain Voltage (V) 1000 10000 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRFIB8N50K 7.0 6.0 V DS VGS RG 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % RD D.U.T. + ID , Drain Current (A) 5.0 4.0 3.0 2.0 1.0 0.0 25 50 75 100 125 150 -VDD Fig 10a. Switching Time Test Circuit VDS 90% TC , Case Temperature ( °C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 10 Thermal Response (Z thJC ) D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.001 0.01 0.1 1 10 PDM t1 t2 0.01 0.00001 0.0001 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFIB8N50K 700 EAS , Single Pulse Avalanche Energy (mJ) 600 500 400 ID 3.0A 4.2A BOTTOM 6.7A TOP 15V VDS L DRIVER 300 RG D.U.T IAS 20V 200 100 0 25 50 75 100 125 150 tp + - VDD A 0.01Ω Fig 12c. Unclamped Inductive Test Circuit Starting T J , Junction Temperature (°C) Fig 12a. Maximum Avalanche Energy Vs. Drain Current tp V(BR)DSS I AS Fig 12d. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ 12V .2µF .3µF QG VGS D.U.T. + V - DS QGS VG QGD VGS 3mA IG ID Current Sampling Resistors Charge Fig 13a. Gate Charge Test Circuit Fig 13b. Basic Gate Charge Waveform 6 www.irf.com IRFIB8N50K Peak Diode Recovery dv/dt Test Circuit D.U.T + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET® Power MOSFETs www.irf.com 7 IRFIB8N50K TO-220 Full-Pak Package Outline Dimensions are shown in millimeters (inches) 10.60 (.417) 10.40 (.409) 3.40 (.133) 3.10 (.123) - A3.70 (.145) 3.20 (.126) 4.80 (.189) 4.60 (.181) ø 2.80 (.110) 2.60 (.102) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 7.10 (.280) 6.70 (.263) 16.00 (.630) 15.80 (.622) 1.15 (.045) MIN. 1 2 3 NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982 2 CONTROLLING DIMENSION: INCH. 3.30 (.130) 3.10 (.122) -B13.70 (.540) 13.50 (.530) C D A 3X 1.40 (.055) 1.05 (.042) 3X 0.90 (.035) 0.70 (.028) 0.25 (.010) 2.54 (.100) 2X M A M B 3X 0.48 (.019) 0.44 (.017) B 2.85 (.112) 2.65 (.104) MINIMUM CREEPAGE DISTANCE BETW EEN A-B-C-D = 4.80 (.189) TO-220 Full-Pak Part Marking Information à B  # ' D A S D à I 6 à T D à T D C U ) @ G Q H 6 Y @ TO-22O Full-Pak package is not recommended for Surface Mount Application. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 04/04 à ` G 7 H @ T T 6 à C U D X ! " # " à @ 9 P 8 à U P G ( ( ( à # ! à X X à I P à 9 @ G 7 H @ T T 6 Å F Å Ã @ I D G à ` G 7 H @ T T 6 à @ C U à I D S @ 7 H V I à U S 6 Q Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. G 6 I P D U 6 I S @ U I D S @ D A D U 8 @ S P B P G ` G 7 H @ T T 6 @ 9 P 8 à U P G B  # ' D A S D F # ! ( ! " à à à à à à à à à # " à @ 9 P 8 à @ U 6 9 ( ( ( à 2 à ( à S 6 @ ` # ! à F @ @ X F à @ I D G 8 www.irf.com