Power MOSFET

PD - 97050 IRF7823PbF HEXFET® Power MOSFET Applications l High Frequency Point-of-Load Synchronous Buck Converter for Applications in Networking & Computing Systems l Optimized for Control FET applications Benefits l Very Low RDS(on) at 4.5V VGS l Low Gate Charge l Fully Characterized Avalanche Voltage and Current l 100% Tested for RG www.DataSheet4U.com VDSS 30V RDS(on) max Qg 8.7m:@VGS = 10V 9.1nC A A D D D D S S S G 1 2 3 4 8 7 6 5 Top View SO-8 Absolute Maximum Ratings Parameter VDS VGS ID @ TA = 25°C ID @ TA = 70°C IDM PD @TA = 25°C PD @TA = 70°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Max. 30 ± 20 13 11 100 2.5 1.6 0.02 -55 to + 150 Units V f f c A W W/°C °C Linear Derating Factor Operating Junction and Storage Temperature Range Thermal Resistance RθJL RθJA g Junction-to-Ambient fg Junction-to-Drain Lead Parameter Typ. ––– ––– Max. 20 50 Units °C/W Notes  through … are on page 10 www.irf.com 1 10/06/05 IRF7823PbF Static @ TJ = 25°C (unless otherwise specified) Parameter BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th) IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss Rg td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Parameter Single Pulse Avalanche Energy Avalanche Current Min. Typ. Max. Units 30 ––– ––– ––– 1.35 ––– ––– ––– ––– ––– 27 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 0.024 6.9 9.3 1.8 -5.1 ––– ––– ––– ––– ––– 9.1 2.7 0.84 3.2 2.4 4.0 5.8 2.0 7.2 8.2 10 2.7 1110 240 110 ––– ––– 8.7 11.9 2.35 ––– 1.0 150 100 -100 ––– 14 ––– ––– ––– ––– ––– ––– 3.0 ––– ––– ––– ––– ––– ––– ––– Typ. ––– ––– pF ns nC Ω nC VDS = 15V VGS = 4.5V ID = 10A S nA V mV/°C µA V mΩ Conditions VGS = 0V, ID = 250µA VGS = 10V, ID = 13A VGS = 4.5V, ID = 10A V/°C Reference to 25°C, ID = 1mA VDS = VGS, ID = 25µA VDS = 24V, VGS = 0V e e VDS = 24V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VDS = 15V, ID = 10A See Fig. 17 & 18 VDS = 16V, VGS = 0V VDD = 16V, VGS = 4.5V ID = 10A Clamped Inductive Load See Fig. 15 VGS = 0V VDS = 15V ƒ = 1.0MHz Max. 230 10 Units mJ A Avalanche Characteristics EAS IAR ™ d Diode Characteristics Parameter IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ù Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units ––– ––– ––– ––– ––– ––– ––– ––– 7.8 9.0 3.1 A 100 1.0 12 14 V ns nC Conditions MOSFET symbol showing the integral reverse G S D p-n junction diode. TJ = 25°C, IS = 10A, VGS = 0V TJ = 25°C, IF = 10A, VDD = 15V Fig. 16 di/dt = 500A/µs e eÃSee Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com IRF7823PbF 1000 TOP VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V 2.3V 1000 TOP VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V 2.3V ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 100 BOTTOM 100 BOTTOM 10 10 1 1 2.3V 0.1 2.3V 0.01 0.1 1 ≤60µs PULSE WIDTH Tj = 25°C 0.1 100 0.1 1 10 ≤60µs PULSE WIDTH Tj = 150°C 10 100 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) ID = 13A VGS = 10V 100 1.5 10 T J = 150°C 1 VDS = 15V ≤60µs PULSE WIDTH 0.1 1 2 3 4 5 T J = 25°C 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3 IRF7823PbF 10000 VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED 12.0 ID= 10A VGS, Gate-to-Source Voltage (V) Crss = C gd Coss = Cds + Cgd 10.0 8.0 6.0 4.0 2.0 0.0 C, Capacitance (pF) 1000 Ciss VDS= 24V VDS= 15V Coss 100 Crss 10 1 10 VDS, Drain-to-Source Voltage (V) 100 0 2 4 6 8 10 12 14 16 18 20 QG, Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) ISD, Reverse Drain Current (A) ID, Drain-to-Source Current (A) 100 T J = 150°C 10 T J = 25°C 100 100µsec 10 1msec 1 10msec 1 VGS = 0V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-to-Drain Voltage (V) 0.1 T A = 25°C Tj = 150°C Single Pulse 0 1 10 100 0.01 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRF7823PbF 14 12 ID, Drain Current (A) VGS(th) , Gate Threshold Voltage (V) 2.5 10 8 6 4 2 0 25 50 75 100 125 150 T A , Ambient Temperature (°C) 2.0 1.5 ID = 50µA 1.0 0.5 -75 -50 -25 0 25 50 75 100 125 150 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature 100 10 Thermal Response ( Z thJA ) 1 0.1 0.01 0.001 D = 0.50 0.20 0.10 0.05 0.02 0.01 τJ τJ τ1 τ1 R1 R1 τ2 R2 R2 R3 R3 τA τ3 τA τ2 τ3 C i= τi/R i C i= τi/R i Ri (°C/W) τi (sec) 7.520 0.013427 25.573 1.1097 16.913 36.9 SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Ta 0.0001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100 1000 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 5 IRF7823PbF RDS(on), Drain-to -Source On Resistance (m Ω) 30 ID = 13A 25 20 15 10 5 0 2 4 6 8 10 T J = 25°C 1000 EAS , Single Pulse Avalanche Energy (mJ) 800 ID TOP 0.82A 1.1A BOTTOM 10A 600 T J = 125°C 400 200 0 25 50 75 100 125 150 Starting T J , Junction Temperature (°C) VGS, Gate -to -Source Voltage (V) Fig 12. On-Resistance vs. Gate Voltage Fig 13. Maximum Avalanche Energy vs. Drain Current LD 15V VDS VDS L DRIVER VDD D.U.T RG VGS 20V D.U.T IAS tp + V - DD VGS A 0.01Ω Pulse Width < 1µs Duty Factor < 0.1% Fig 14a. Unclamped Inductive Test Circuit V(BR)DSS tp Fig 15a. Switching Time Test Circuit 90% VDS 10% VGS I AS td(on) tf td(off) tr Fig 14b. Unclamped Inductive Waveforms Fig 15b. Switching Time Waveforms 6 www.irf.com IRF7823PbF D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Current Regulator Same Type as D.U.T. Id Vds Vgs 50KΩ 12V .2µF .3µF D.U.T. VGS 3mA + V - DS Vgs(th) IG ID Qgs1 Qgs2 Qgd Qgodr Current Sampling Resistors Fig 17. Gate Charge Test Circuit Fig 18. Gate Charge Waveform www.irf.com 7 IRF7823PbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by; * P =P loss conduction + P drive + P output P = Irms × Rds(on) loss + (Qg × Vg × f ) ( 2 ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput This can be expanded and approximated by; ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝2 ⎠ *dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Ploss = (Irms × Rds(on ) ) 2 ⎛ ⎞⎛ Qgs 2