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Part Number |
IRF540ZPBF |
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Manufacturer |
International Rectifier |
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Semiconductor DataSheet |
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DataSheet View |
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PD - 95531
AUTOMOTIVE MOSFET
IRF540ZPbF IRF540ZSPbF IRF540ZLPbF
HEXFET® Power MOSFET
D
Features
l l l l l l
Advanced Process Technology Ultra Low On-Resistance 175°C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free
VDSS = 100V RDS(on) = 26.5mΩ
G S
Specifically designed for Automotive applications, this HEXFET® Power MOSFET utilizes the latest processing techniques to achieve extremely low onresistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications.
Description
ID = 36A
TO-220AB IRF540Z
D2Pak IRF540ZS
TO-262 IRF540ZL
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) ID @ TC = 100°C Continuous Drain Current, VGS @ 10V Pulsed Drain Current IDM
Max.
36 25 140 92 0.61 ± 20
Units
A W W/°C V mJ A mJ
PD @TC = 25°C Power Dissipation Linear Derating Factor VGS Gate-to-Source Voltage EAS (Thermally limited) Single Pulse Avalanche Energyd Single Pulse Avalanche Energy Tested Value EAS (Tested ) IAR EAR TJ TSTG Avalanche Currentà Repetitive Avalanche Energy Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting Torque, 6-32 or M3 screw
h
83 120 See Fig.12a, 12b, 15, 16 -55 to + 175
g i
°C 300 (1.6mm from case ) 10 lbfyin (1.1Nym)
Thermal Resistance
Parameter
RθJC RθCS RθJA RθJA Junction-to-Case Case-to-Sink, Flat Greased Surface Junction-to-Ambient
Typ.
Max.
1.64 ––– 62 40
Units
°C/W
i
i
––– 0.50 ––– –––
Junction-to-Ambient (PCB Mount)
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j
1
7/20/04
IRF540Z/S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff. Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance
Min. Typ. Max. Units
100 ––– ––– 2.0 36 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 0.093 21 ––– ––– ––– ––– ––– ––– 42 9.7 15 15 51 43 39 4.5 7.5 1770 180 100 730 110 170 ––– ––– 26.5 4.0 ––– 20 250 200 -200 63 ––– ––– ––– ––– ––– ––– ––– nH ––– ––– ––– ––– ––– ––– ––– pF ns nC nA V
Conditions
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 22A V V µA VDS = VGS, ID = 250µA VDS = 25V, ID = 22A VDS = 100V, VGS = 0V VDS = 100V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V ID = 22A VDS = 80V VGS = 10V VDD = 50V ID = 22A RG = 12 Ω VGS = 10V
e
e e
Between lead, 6mm (0.25in.) from package and center of die contact VGS = 0V VDS = 25V ƒ = 1.0MHz
G
D
S
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz VGS = 0V, VDS = 80V, ƒ = 1.0MHz VGS = 0V, VDS = 0V to 80V
f
Source-Drain Ratings and Characteristics
Parameter
IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ã Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
––– ––– ––– ––– ––– ––– ––– ––– 33 41 36 A 140 1.3 50 62 V ns nC
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25°C, IS = 22A, VGS = 0V TJ = 25°C, IF = 22A, VDD = 50V di/dt = 100A/µs
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRF540Z/S/LPbF
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
100
BOTTOM
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
BOTTOM
10
10
4.5V
4.5V
1 0.1 1
60µs PULSE WIDTH Tj = 25°C
10 100
60µs PULSE WIDTH Tj = 175°C
1 0.1 0
1
10
100 100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
80
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (Α)
T J = 175°C 60
100
T J = 175°C
40 T J = 25°C 20 VDS = 10V 380µs PULSE WIDTH 0 0 10 20 30 40 50 ID, Drain-to-Source Current (A)
10
T J = 25°C VDS = 25V 60µs PULSE WIDTH
1 4.0 5.0 6.0 7.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance Vs. Drain Current
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3
IRF540Z/S/LPbF
3000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
20
VGS, Gate-to-Source Voltage (V)
ID= 22A VDS= 80V VDS= 50V VDS= 20V
2500
16
C, Capacitance (pF)
2000
Ciss
12
1500
8
1000
500
4
FOR TEST CIRCUIT SEE FIGURE 13
Coss Crss
0 1 10 100
0 0 10 20 30
40
50
60
VDS, Drain-to-Source Voltage (V)
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000.0
1000
OPERATION IN THIS AREA LIMITED BY R DS(on)
ISD, Reverse Drain Current (A)
100.0 T J = 175°C 10.0
ID, Drain-to-Source Current (A)
100
10
100µsec
1.0 T J = 25°C VGS = 0V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VSD, Source-toDrain Voltage (V)
1 Tc = 25°C Tj = 175°C Single Pulse 1 10 1msec 10msec 100 1000
0.1
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF540Z/S/LPbF
40 3.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
2.5
ID = 22A VGS = 10V
ID , Drain Current (A)
30
2.0
20
1.5
10
1.0
0 25 50 75 100 125 150 175
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
T J , Junction Temperature (°C)
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10. Normalized On-Resistance Vs. Temperature
10
Thermal Response ( Z thJC )
1
D = 0.50 0.20 0.10
0.1
0.05 0.02 0.01
0.01
SINGLE PULSE ( THERMAL RESPONSE )
0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF540Z/S/LPbF
EAS , Single Pulse Avalanche Energy (mJ)
15V
180 160 140 120 100 80 60 40 20 0 25 50 75 100 125 150 175
VDS
L
DRIVER
ID 8.3A 14A BOTTOM 20A TOP
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
Starting T J , Junction Temperature (°C)
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
10 V
QGS
QGD
VGS(th) Gate threshold Voltage (V)
4.0
VG
3.5
Charge
3.0
ID = 250µA
Fig 13a. Basic Gate Charge Waveform
2.5
L
0
2.0
DUT 1K
VCC
1.5 -75 -50 -25 0 25 50 75 100 125 150 175
T J , Temperature ( °C )
Fig 13b. Gate Charge Test Circuit
Fig 14. Threshold Voltage Vs. Temperature
6
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IRF540Z/S/LPbF
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
0.01
10
Allowed avalanche Current vs avalanche pulsewidth, tav assuming ∆ Tj = 25°C due to avalanche losses
0.05 0.10
1
0.1 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
100 90
EAR , Avalanche Energy (mJ)
80 70 60 50 40 30 20 10 0 25 50
TOP Single Pulse BOTTOM 10% Duty Cycle ID = 20A
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav
Fig 16. Maximum Avalanche Energy Vs. Temperature
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7
IRF540Z/S/LPbF
Driver Gate Drive
D.U.T
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
• • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
RD
VDS VGS RG 10V
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
D.U.T.
+
-VDD
Fig 18a. Switching Time Test Cir |