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PD - 95529
IRF3709ZCSPbF IRF3709ZCLPbF
Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l Lead-Free
HEXFET® Power MOSFET
VDSS RDS(on) max
30V 6.3m:
Qg
17nC
Benefits l Low RDS(on) at 4.5V VGS l Low Gate Charge l Fully Characterized Avalanche Voltage and Current
D2Pak IRF3709ZCS
TO-262 IRF3709ZCL
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C PD @TC = 100°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
Max.
30 ± 20 87 62
Units
V A
c
h h
350 79 40 0.53 -55 to + 175 300 (1.6mm from case) W/°C °C W
Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Thermal Resistance
Parameter
RθJC RθJA Junction-to-Case
i
Typ.
Max.
1.89 40
Units
°C/W
Junction-to-Ambient (PCB Mount)
g
––– –––
Notes through are on page 11
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1
7/20/04
IRF3709ZCS/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
30 ––– ––– ––– 1.35 ––– ––– ––– ––– ––– 88 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 0.021 5.0 6.2 ––– -5.5 ––– ––– ––– ––– ––– 17 4.4 1.7 6.0 4.9 7.7 11 13 41 16 4.7 2130 450 220 ––– ––– 6.3 7.8 2.25 ––– 1.0 150 100 -100 ––– 26 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– pF VGS = 0V VDS = 15V ns nC nC VDS = 15V VGS = 4.5V ID = 17A S nA V mV/°C µA V
Conditions
VGS = 0V, ID = 250µA
mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 21A VGS = 4.5V, ID = 17A
e e
VDS = VGS, ID = 250µA VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VDS = 15V, ID = 17A
See Fig. 14a&b VDS = 16V, VGS = 0V VDD = 15V, VGS = 4.5V ID = 17A Clamped Inductive Load
e
ƒ = 1.0MHz
Avalanche Characteristics
EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current
Ã
d
Typ. ––– ––– –––
Max. 60 17 7.9
Units mJ A mJ
Repetitive Avalanche Energy
––– ––– ––– ––– ––– ––– ––– ––– 16 6.2
Diode Characteristics
Parameter
IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
Min. Typ. Max. Units
87
h
Conditions
MOSFET symbol
D
A 350 1.0 24 9.3 V ns nC
Ã
showing the integral reverse
G S
p-n junction diode. TJ = 25°C, IS = 17A, VGS = 0V TJ = 25°C, IF = 17A, VDD = 15V di/dt = 100A/µs
e
e
2
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IRF3709ZCS/LPbF
1000
TOP VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V 3.0V
1000
TOP VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V 3.0V
ID, Drain-to-Source Current (A)
BOTTOM
ID, Drain-to-Source Current (A)
100
BOTTOM
100
3.0V
10
3.0V
≤60µs PULSE WIDTH
10 0.1 1 Tj = 25°C 1 100 0.1 1 10
≤60µs PULSE WIDTH
Tj = 175°C 10 100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance (Normalized)
2.0
ID, Drain-to-Source Current (Α)
ID = 42A VGS = 10V
100
T J = 175°C
1.5
10
1.0
1
T J = 25°C VDS = 15V ≤60µs PULSE WIDTH 0 1 2 3 4 5 6 7 8
0.1
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
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IRF3709ZCS/LPbF
10000 VGS = 0V, f = 1 MHZ C iss = C gs + Cgd, C ds SHORTED C rss = C gd C oss = C ds + Cgd
6.0 ID= 17A
VGS, Gate-to-Source Voltage (V)
5.0 4.0 3.0 2.0 1.0 0.0
C, Capacitance(pF)
Ciss
1000
VDS= 24V VDS= 15V
Coss
Crss
100 1 10 100
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
1000.00
10000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100.00
T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100
100µsec
10 1msec 1 Tc = 25°C Tj = 175°C Single Pulse 0 1 10 10msec
10.00
T J = 25°C
VGS = 0V 1.00 0.0 0.5 1.0 1.5 2.0 2.5 VSD, Source-to-Drain Voltage (V)
0.1 100 1000 VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF3709ZCS/LPbF
90 Limited By Package
VGS(th) Gate threshold Voltage (V)
2.5
80 70
ID, Drain Current (A)
2.0
60 50 40 30 20 10 0 25 50 75 100 125 150 175 T C , Case Temperature (°C)
1.5
ID = 250µA
1.0
0.5 -75 -50 -25 0 25 50 75 100 125 150 175 200
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10. Threshold Voltage vs. Temperature
10
Thermal Response ( Z thJC )
1
D = 0.50 0.20
0.1
0.10 0.05 0.02 0.01
τJ
R1 R1 τJ τ1 τ2
R2 R2 τC τ τ2
Ri (°C/W) τi (sec) 0.832 0.000221 1.058 0.001171
τ1
0.01
SINGLE PULSE ( THERMAL RESPONSE )
Ci= τi/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.0001 0.001 0.01 0.1
0.001 1E-006 1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRF3709ZCS/LPbF
RDS(on), Drain-to -Source On Resistance ( mΩ)
Vgs = 10V
8.00
RDS(on), Drain-to -Source On Resistance (m Ω)
9.00
16 14 12 10 8 6 4 2 0 2 3 4 5 6 7 8 9 10 T J = 25°C T J = 125°C ID = 21A
T J = 125°C
7.00
6.00
T J = 25°C
5.00
4.00 10.0 20.0 30.0 40.0 50.0 60.0 70.0
ID, Drain Current (A)
VGS, Gate -to -Source Voltage (V)
Fig 12. On-Resistance vs. Drain Current
Current Regulator Same Type as D.U.T.
Id Vds
50KΩ 12V .2µF .3µF
Fig 13. On-Resistance vs. Gate Voltage
Vgs
250
D.U.T. VGS
3mA
EAS , Single Pulse Avalanche Energy (mJ)
+ V - DS
Vgs(th)
200
ID 5.4A 8.0A BOTTOM 17A TOP
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
150
Fig 14a&b. Basic Gate Charge Test Circuit and Waveform
15V
100
V(BR)DSS tp
VDS L
50
DRIVER
RG
20V
D.U.T
IAS
+ V - DD
0
A
25
50
75
100
125
150
175
I AS
tp
0.01Ω
Starting T J , Junction Temperature (°C)
Fig 15a&b. Unclamped Inductive Test circuit and Waveforms
Fig 16. Maximum Avalanche Energy vs. Drain Current
6
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IRF3709ZCS/LPbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
• • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
LD VDS
+
VDD D.U.T VGS Pulse Width < 1µs Duty Factor < 0.1%
Fig 18a. Switching Time Test Circuit
90%
VDS
10%
VGS
td(on) tr td(off) tf
Fig 18b. Switching Time Waveforms
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IRF3709ZCS/LPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by;
* P =P loss conduction + P drive + P output
P = Irms × Rds(on) loss
+ (Qg × Vg × f )
(
2
)
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎠ ⎝ 2
*dissipated primarily in Q1.
Ploss = (Irms × Rds(on ) )
2
⎛ ⎞ ⎛ Qgs 2 Qgd +⎜I× × Vin × f ⎟ + ⎜ I × × Vin × ig ig ⎝ ⎠ ⎝ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠
⎞ f⎟ ⎠
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the p
