64-pin CK505 w/Fully Integrated Voltage Regulator

www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9LPR501 64-pin CK505 w/Fully Integrated Voltage Regulator Recommended Application: CK505 compliant clock with fully integrated voltage regulator Output Features: • 2 - CPU differential low power push-pull pairs • 10 - SRC differential low power push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair • 1 - SRC/DOT selectable differential low power push-pull pair • 5 - PCI, 33MHz • 1 - PCI_F, 33MHz free running • 1 - USB, 48MHz • 1 - REF, 14.318MHz Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 100ppm frequency accuracy on CPU & SRC clocks Features/Benefits: • Does not require external pass transistor for voltage regulator • Supports spread spectrum modulation, default is 0.5% down spread • • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Selectable between one SRC differential push-pull pair and two single-ended outputs Pin Configuration PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/TME PCI3 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 DOTC_96/SRCC0 GND VDD SRCT1/SE1 SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC SRCT3/CR#_C SRCC3/CR#_D VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9 SRCC11/CR#_G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0 CPUC0 GNDCPU CPUT1_F CPUC1_F VDDCPU_IO NC CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 VDDSRC_IO SRCT7/CR#_F SRCC7/CR#_E GNDSRC SRCT6 SRCC6 VDDSRC PCI_STOP#/SRCT5 CPU_STOP#/SRCC5 VDDSRC_IO SRCC10 SRCT10 SRCT11/CR#_H 64-pin TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor Table 1: CPU Frequency Select Table FS LC B0b7 0 0 0 0 1 1 1 1 2 FS LB B0b6 0 0 1 1 0 0 1 1 1 FSLA B0b5 0 1 0 1 0 1 0 1 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 SRC MHz PCI MHz REF MHz USB MHz DOT MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. 1118E—08/08/07 9LPR501 www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9LPR501 Pin Description PIN # PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 37 and 38). The latched value controls the pin function on pins 37 and 38 as follows 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs. Power supply for DOT96 outputs, VDD96_IO is 1.05 to 3.3V with +/-5% tolerance True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 0= SRC0 1=DOT96 Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows 0= SRC0# 1=DOT96# Ground pin for the DOT96 clocks. Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. 1 PCI0/CR#_A I/O 2 VDDPCI PWR 3 PCI1/CR#_B I/O 4 PCI2/TME I/O 5 PCI3 OUT 6 PCI4/SRC5_EN I/O 7 PCI_F5/ITP_EN I/O 8 9 10 11 12 13 GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 PWR PWR I/O PWR PWR OUT 14 DOTC_96/SRCC0 OUT 15 16 GND VDD PWR PWR 1118E—08/08/07 2 www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9LPR501 Pin Description (Continued) PIN # 17 18 19 20 21 22 23 PIN NAME SRCT1/SE1 SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC TYPE OUT OUT PWR PWR OUT OUT PWR DESCRIPTION True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Ground pin for SRC / SE1 and SE2 clocks, PLL3. Power supply for PLL3 output. VDDPLL3_IO is 1.05 to 3.3V with +/-5% tolerance True clock of differential SRC/SATA clock pair. Complement clock of differential SRC/SATA clock pair. Ground pin for SRC clocks. True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default), 1= CR#_D controls SRC4 pair Power supply for SRC clocks. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance True clock of differential SRC clock pair 4 Complement clock of differential SRC clock pair 4 Ground pin for SRC clocks. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. SRC11 complement /Clock Request control for SRC9 pair The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9 24 SRCT3/CR#_C I/O 25 SRCC3/CR#_D I/O 26 27 28 29 30 31 VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9 PWR I/O I/O PWR OUT OUT 32 SRCC11/CR#_G I/O 1118E—08/08/07 3 www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9LPR501 Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION SRC11 true or Clock Request control H for SRC10 pair The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3 bit 7 of SMBus configuration space Aft