System Clock Chip

www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS951412 System Clock Chip for ATI RS480 K8-based Systems Recommended Application: ATI RS480 systems using AMD K8 processors Output Features: • 3 - 14.318 MHz REF clocks • 1 - USB_48MHz USB clock • 1 - HyperTransport 66 MHz clock seed • 1 - PCI 33 MHz clock seed • 2 - Pairs of AMD K8 clocks • 6 - Pairs of SRC/PCI Express* clocks • 2 - Pairs of ATIG (SRC/PCI Express) clocks Features: • 2 - Programmable Clock Request pins for SRC clocks • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • External crystal load capacitors for maximum frequency accuracy Pin Configuration X1 X2 VDD48 USB_48MHz GND NC SCLK SDATA **FS2 **CLKREQA# **CLKREQB# SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GNDSRC VDDSRC SRCCLKT4 SRCCLKC4 SRCCLKT3 SRCCLKC3 GNDSRC ATIGCLKT1 ATIGCLKC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDREF GND **FS0/REF0 **FS1/REF1 REF2 VDDPCI PCICLK0 GNDPCI VDDHTT HTTCLK0 GNDHTT CPUCLK8T0 CPUCLK8C0 VDDCPU GNDCPU CPUCLK8T1 CPUCLK8C1 VDDA GNDA IREF GNDSRC VDDSRC SRCCLKT0 SRCCLKC0 VDDATI GNDATI ATIGCLKT0 ATIGCLKC0 Note: Pins preceeded by '**' have a 120 Kohm Internal Pull Down resistor 56 Pin SSOP/TSSOP Power Groups Pin Number VDD 56 51 48 43 14, 21, 32,35 39 3 GND 55 49 46 42 15, 20, 26,31,36 38 5 Description Xtal, REF PCICLK output HTTCLK output CPU Outputs SRC outputs Analog, CPU PLL USB_48MHz output Functionality FS2 0 0 0 0 1 1 1 FS1 0 0 1 1 0 0 1 FS0 0 1 0 1 0 1 1 CPU MHz Hi-Z X 180.00 220.00 100.00 133.33 200.00 HTT MHz Hi-Z X/3 60.00 73.12 66.66 66.66 66.66 PCI MHz Hi-Z X/6 30.00 36.56 33.33 33.33 33.33 0883G—12/08/04 *Other names and brands may be claimed as the property of others. ICS951412 www.DataSheet4U.com ICS951412 Pin Descriptions PIN # 1 2 3 4 5 6 7 8 9 10 PIN NAME X1 X2 VDD48 USB_48MHz GND NC SCLK SDATA **FS2 **CLKREQA# PIN TYPE IN OUT PWR OUT PWR N/A IN I/O IN IN DESCRIPTION Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power pin for the 48MHz output.3.3V 48.00MHz USB clock Ground pin. No Connection. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Frequency select pin. Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Ground pin for the SRC outputs Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Ground pin for the SRC outputs True clock of differential SRC clock pair. Complementary clock of differential SRC clock pair. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 **CLKREQB# SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GNDSRC VDDSRC SRCCLKT4 SRCCLKC4 SRCCLKT3 SRCCLKC3 GNDSRC ATIGCLKT1 ATIGCLKC1 IN OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR OUT OUT 0883G—12/08/04 2 www.DataSheet4U.com ICS951412 Pin Descriptions (Continued) PIN # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 PIN NAME ATIGCLKC0 ATIGCLKT0 GNDATI VDDATI SRCCLKC0 SRCCLKT0 VDDSRC GNDSRC IREF GNDA VDDA CPUCLK8C1 CPUCLK8T1 GNDCPU VDDCPU CPUCLK8C0 CPUCLK8T0 GNDHTT HTTCLK0 VDDHTT GNDPCI PCICLK0 VDDPCI REF2 **FS1/REF1 **FS0/REF0 GND VDDREF TYPE OUT OUT PWR PWR OUT OUT PWR PWR OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR OUT PWR PWR OUT PWR OUT I/O I/O PWR PWR DESCRIPTION Complementary clock of differential SRC clock pair. True clock of differential SRC clock pair. Ground for ATI Gclocks, nominal 3.3V Power supply ATI Gclocks, nominal 3.3V Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin for the CPU outputs Supply for CPU clocks, 3.3V nominal Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin for the HTT outputs 3.3V Hyper Transport output Supply for HTT clocks, nominal 3.3V. Ground pin for the PCI outputs PCI clock output. Power supply for PCI clocks, nominal 3.3V 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Ground pin. Ref, XTAL power supply, nominal 3.3V 0883G—12/08/04 3 www.DataSheet4U.com ICS951412 General Description The ICS951412 is a main clock synthesizer chip that provides all clocks required for ATI RS480-based systems. An SMBus interface allows full control of the device. Block Diagram REF(2:0) X1 X2 XTAL OSC. FIXED PLL DIVIDER USB_48MHz PCICLK0 HTTCLK0 SRCCLK(7:3,0) MAIN PLL DIVIDERS ATIGCLK(1:0) CPUCLK8(1:0) FS(2:0) CLKREQA# CLKREQB# SEL75#/100 SDATA SCLK CONTROL LOGIC IREF Skew Characteristics Parameter Tsk_CPU_CPU Tsk_CPU_PCI Tsk_PCI_PCI Tsk_PCI33-HT66 Tsk_CPU_HT66 Tsk_CPU_HT66 Tsk_CPU_CPU Tsk_CPU_PCI Tsk_PCI_PCI Tsk_PCI33-HT66 Tsk_CPU_HT66 Tsk_CPU_HT66 0883G—12/08/04 Description Test Conditons measured at x-ing of CPU, measured at x-ing of CPU, 1.5V of PCI clock measured between rising edge at 1.5V measured between rising edge at 1.5V measured between rising edge at 1.5V measured at x-ing of CPU, 1.5V of PCI clock measured at x-ing of CPU, measured at x-ing of CPU, 1.5V of PCI clock measured between rising edge at 1.5V measured between rising edge at 1.5V measured between rising edge at 1.5V measured at x-ing of CPU, 1.5V of PCI clock Skew Window 250 2000 500 500 2000 500 200 200 200 200 200 200 Unit ps ps ps ps ps ps ps ps ps ps ps ps time independent skew not dependent on V, T changes time variant skew varies over V, T changes 4 www.DataSheet4U.com ICS951412 General SMBus serial interface information How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P 0883G—12/08/04 Not acknowledge stoP bit 5 www.DataSheet4U.com ICS951412 Table1: CPU Frequency Selection Table CPU CPU Bit2 Bit1 Bit0 CPU FS4 FS3 FS2 FS1 FS0 (MHz) (B0:b4) (B0:b3) 0 0 0 0 0 Hi-Z 0 0 0 0 1 X/6 0 0 0 1 0 180.00 0 0 0 1 1 220.00 0 0 1 0 0 100.00 0 0 1 0 1 133.33 0 0 1 1 0 166.67 0 0 1 1 1 200.00 0 1 0 0 0 186.00 0 1 0 0 1 214.00 0 1 0 1 0 190.00 0 1 0 1 1 210.00 0 1 1 0 0 102.00 0 1 1 0 1 136.00 0 1 1 1 0 170.00 0 1 1 1 1 204.00 1 0 0 0 0 169.58 1 0 0 0 1 229.43 1 0 0 1 0 179.55 1 0 0 1 1 219.45 1 0 1 0 0 99.75 1 0 1 0 1 133.00 1 0 1 1 0 166.25 1 0 1 1 1 199.50 1 1 0 0 0 185.54 1 1 0 0 1 106.73 1 1 0 1 0 189.53 1 1 0 1 1 209.48 1 1 1 0 0 101.75 1 1 1 0 1 135.66 1 1 1 1 0 169.58 1 1 1 1 1 203.49 HTT66 PCI33 (MHz) (MHz) Hi-Z X/12 60.00 73.33 66.67 66.67 66.67 66.67 62.00 71.33 63.33 70.00 68.00 68.00 68.00 68.00 56.53 76.48 59.85 73.15 66.50 66.50 66.50 66.50 61.85 71.16 63.18 69.83 67.83 67.83 67.83 67.83 Hi-Z X/24 30.00 36.67 33.33 33.33 33.33 33.33 31.00 35.67 31.67 35.00 34.00 34.00 34.00 34.00 28.26 38.24 29.93 36.58 33.25 33.25 33.25 33.25 30.92 35.58 31.59 34.91 33.92 33.91 33.92 33.92 Spread % None None None None None None None None None None None None None None None None -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% 0883G—12/08/04 6 www.DataSheet4U.com ICS951412 SMBus Table: Frequency Select Register Byte 0 Pin # Name Control Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FS Source SS_EN Reserved FS4 FS3 FS2 FS1 FS0 Type 0 La