AMD-K7 System Clock Chip

www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS951403 AMD-K7TM System Clock Chip Recommended Application: ATI chipset with K7 systems Output Features: • 3 differential pair open drain CPU clocks (1.5V external pull-up; up to 150MHz achieviable through I2C) • 2 - AGPCLK @ 3.3V • 8 - PCI @3.3V, including 1 free running • 1 - 48MHz @ 3.3V • 1 - 24/48MHz @ 3.3V • 2- REF @3.3V, 14.318MHz. Features: • Programmable ouput frequency • Programmable ouput rise/fall time • Programmable group skew • Real time system reset output • Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage • Watchdog timer technology to reset system if over-clocking causes malfunction • Uses external 14.318MHz crystal • Asyncronous CPU and SDRAM clocks • CPU and PCI outputs are aligned • CPU - AGP skew <500ps Pin Configuration 48-Pin SSOP & TSSOP * Internal 120K pullup resistor on indicated inputs ** Internal 240K pullup resistor on indicated inputs Block Diagram PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz Functionality Bit 7 FS2 0 0 REF (1:0) FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 100.00 100.00 100.00 100.00 133.33 125.00 124.00 133.33 112.00 150.00 111.11 110.00 166.67 90.00 48.00 45.00 SDRAM 100.00 133.33 150.00 66.67 133.33 100.00 124.00 100.00 112.00 150.00 166.67 165.00 166.67 90.00 48.00 60.00 PCICLK 33.33 33.33 30.00 33.33 33.33 31.25 31.00 33.33 33.60 30.00 33.33 33.00 33.33 30.00 32.00 30.00 AGP SEL = AGP SEL = 0 1 66.67 66.67 60.00 66.67 66.67 62.50 62.00 66.67 67.20 60.00 66.67 66.00 66.67 60.00 64.00 60.00 50.00 50.00 50.00 50.00 50.00 50.00 46.50 50.00 56.00 50.00 55.56 55.00 55.56 45.00 48.00 45.00 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CPU DIVDER Stop 3 3 CPUCLKT (2:0) CPUCLKC (2:0) SDRAM_OUT SDRAM DIVDER SEL24_48# SDATA Control SCLK FS (2:0) PD# PCI_STOP# CPU_STOP# SPREAD# Config. Reg. Logic AGP DIVDER 2 PCI DIVDER Stop 7 PCICLK (6:0) PCICLK_F AGP (1:0) Power Groups VDD48, GND48 = 48MHz, PLL2 VDDREF, GNDREF= REF, X1, X2 VDD, GND = PLL Core 0486B—02/23/04 www.DataSheet4U.com ICS951403 General Description The ICS951403 is a main clock synthesizer chip for AMD-K7 based systems with ATI chipset. This provides all clocks required for such a system. The ICS951403 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/ enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking. Pin Descriptions PIN NUMBER 2,1 3, 6, 21, 25, 33, 38, 41, 47 4 5 7 17, 16, 14, 13, 11, 10, 8 9, 15 18 20, 19 34 22 23 24 26 27 28 29 30 31 32 35 46 44 42, 39, 36 43, 40, 37 45 48 0486B—02/23/04 PIN NAME FS (1:0) REF (1:0) GND X1 X2 PCICLK_F PCICLK (6:0) VDDPCI VDDAGP AGP (1:0) VDD VDD48 48MHz SEL24-48# 24-48MHz SCLK SDATA FS2 SPREAD# PD# CPU_STOP# PCI_STOP# TYPE IN OUT PWR IN OUT OUT OUT PWR PWR OUT PWR PWR OUT IN OUT IN I/O IN IN IN IN IN DESCRIPTION Frequency Select pins, has pull-up to VDD 14.318MHz clock output Ground XTAL_IN 14.318MHz Cr ystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Cr ystal output, has internal load cap 33pF Free Running PCI output. Not affected by the PCI_STOP# input. PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Power for AGP outputs, nominally 3.3V AGP outputs defined as 2X PCI. These may not be stopped. Isolated power for core, nominally 3.3V Power for 48MHz and 24MHz outputs nominally 3.3V 48MHz output Selects 24 or 48MHz output for pin 24 Low = 48MHz High = 24MHz Fixed clock out selectable through SEL24-48# Clock pin of I2C circuitr y 5V tolerant Data pin for I2C circuitr y 5V tolerant Frequency Select pin, has pull-up to VDD Enables Spread Spectrum feature when LOW. Down Spread 0.5% modulation frequency =50KHz Powers down chip, active low. Internal PLL & all outputs are disabled. Halts CPUCLKs. CPUCLKT is driven LOW wheras CPUCLKC is driven HIGH when this pin is asser ted (Active LOW). Halts PCI Bus at logic "0" level when driven low. PCICLK_F is not affected by this pin RESET# SDRAM_OUT RESERVED CPUCLKT (2:0) CPUCLKC (2:0) VDDSD VDDREF OUT OUT N/C OUT OUT PWR PWR Real time system reset signal for watchdog tmer timeout. This signal is active low. Reference clock for SDRAM zero delay buffer Future CPU power rail "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementar y" clocks of differental pair CPU output. These open drain outputs need an external 1.5V pull_up. Power for SDRAM_OUT pin. Norminally 3.3V Power for REF, X1, X2, nominally 3.3V 2 www.DataSheet4U.com ICS951403 Bit Bit 6 Bit 5 Bit 4 Bit 2 Bit 7 CPU SDRAM FS2 FS1 FS0 0 0 0 0 0 100.00 100.00 0 0 0 0 1 100.00 133.33 0 0 0 1 0 100.00 150.00 0 0 0 1 1 100.00 66.67 0 0 1 0 0 133.33 133.33 0 0 1 0 1 125.00 100.00 0 0 1 1 0 124.00 124.00 0 0 1 1 1 133.33 100.00 0 1 0 0 0 112.00 112.00 0 1 0 0 1 150.00 150.00 0 1 0 1 0 111.11 166.67 0 1 0 1 1 110.00 165.00 0 1 1 0 0 166.67 166.67 0 1 1 0 1 90.00 90.00 0 1 1 1 0 48.00 48.00 Bit 2 Bit 7:4 0 1 1 1 1 45.00 60.00 1 0 0 0 0 100.30 100.30 1 0 0 0 1 100.30 133.73 1 0 0 1 0 105.00 157.50 1 0 0 1 1 100.30 66.87 1 0 1 0 0 110.00 110.00 1 0 1 0 1 103.00 103.00 1 0 1 1 0 103.00 137.33 1 0 1 1 1 133.73 100.30 1 1 0 0 0 133.73 133.73 1 1 0 0 1 140.00 140.00 1 1 0 1 0 137.33 103.00 1 1 0 1 1 137.33 137.33 1 1 1 0 0 105.00 105.00 1 1 1 0 1 138.33 138.33 1 1 1 1 0 200.00 200.00 1 1 1 1 1 104.25 139.00 0 - Frequency is selected by hardware select, Latched Bit 3 1 - Frequency is selected by Bit , 2 7:4 0 - Norm Bit 1 1 - Spreaal Spectrum Enabled d 0 - Running Bit 0 1- Tristate all outputs Description AGP PC I SEL = 0 33.33 66.67 33.33 66.67 30.00 60.00 33.33 66.67 33.33 67.67 31.25 62.50 31.00 62.00 33.33 66.67 33.60 67.20 30.00 60.00 33.33 66.67 33.00 66.00 33.33 66.67 30.00 60.00 32.00 64.00 30.00 60.00 33.43 66.87 33.43 66.87 31.50 63.00 33.43 66.87 33.00 66.00 34.33 68.67 34.33 68.67 33.43 66.87 33.43 66.87 35.00 70.00 34.33 68.67 34.33 68.67 35.00 70.00 34.58 69.17 33.33 66.67 34.75 69.50 Inputs PWD AGP SEL = 1 50.00 50.00 50.00 50.00 50.00 50.00 46.50 50.00 56.00 50.00 55.56 55.00 55.56 45.00 48.00 45.00 50.15 50.15 52.50 50.15 55.00 51.50 51.50 50.15 50.15 52.50 51.50 51.50 52.50 51.88 50.00 52.13 Spread Precentage 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 00000 Note1 0 0 0 Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. Note: PWD = Power-Up Default 0486B—02/23/04 3 www.DataSheet4U.com ICS951403 Byte 1: Output Control Register (1= enable, 0 = disable) Byte 2: PCI Stop Register (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 24 37 36 40 39 43 42 46 PWD 1 1 1 1 1 1 1 1 DESCRIPTION SEL 24/48 0 = 24MHz 1= 48MHz CPUCLKC0 CPUCLKT0 CPUCLKC1 CPUCLKT1 CPUCLKC2 CPUCLKT2 SDRAM_OUT BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 7 17 16 14 13 11 10 8 PWD 1 1 1 1 1 1 1 1 DESCRIPTION PCICLK_F PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Byte 3: CPU Free Running Control Register (1= enable, 0 = disable) Byte 4: 24/48MHz Control Register (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# - PWD X X X X 0 0 0 0 DESCRIPTION Reserved Reserved Reserved Reserved Reserved CPU T/C 0 CPU T/C 1 CPU T/C 2 BIT 7 6 5 4 3 2 1 0 PIN# PWD 24 1 1 1 1 1 1 0 1 DESCRIPTION Reserved 24-48MHz 48MHz Reserved Reserved Reserved AGP frequency select 0 = 66.6MHz 1 = 50.0MHz Reserved Byte 5: Clock Enable Control Register (1= enable, 0 = disable) Byte 6: Control Register (1= enable, 0 = disable) BIT 7 6 5 4 3 2 1 0 Notes: PIN# PWD X X X X 1 2 20 19 1 1 1 1 DESCRIPTION Reserved FS2 Read-back FS1 Read-back FS0 Read-back REF1 REF0 AGP1 AGP0 BIT 7 6 5 4 3 2 1 0 Notes: PIN# PWD 0 0 0 X X X X 0 DESCRIPTION REF strength 0 = 1X 1 = 2X 0 = CPU C1:2, T1:2 stop 1 = CPU C1:2, T1:2 free running Reserved SPREAD# read-back CPU_STOP# read-back PCI_STOP# read-back Reserved AGP speed toggle 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 0486B—02/23/04 3. Bytes 7:14 not defined. 4 www.DataSheet4U.com ICS951403 Byte 15: CPU_SDRAM Skew Register Byte 16: Slew Rate Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 1 0 0 1 1 1 1 0 Description SDRAM (pdel canned) Reserved CPUC0 & T0 (pdel canned) CPUC 1:2 & T 1:2 (pdel canned) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Byte 17: Slew Rate Control Register Byte 18: Slew Rate Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 1 0 1 0 1 0 1 0 Description PCI (3:0) Slew Control PCI_F Sl