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ICS951402 Advance Information
Programmable Timing Control Hub™ for P4™ processor
Recommended Application: ATI chipset, P4 system, Banias system Output Features: • 2 - Pairs of differential CPUCLKs (differential current mode) • 1 - SDRAM @ 3.3V • 8 - PCI @3.3V (selectable 33/66 MHz) (2 free-running) • 2 - AGP @ 3.3V • 2- 48MHz, @3.3V fixed. • 1- 24/48MHz, @3.3V selectable by I2C (Default is 24MHz) • 3- REF @3.3V, 14.318MHz. Features/Benefits: • Support for Intel Banias power management features • Programmable output frequency, divider ratios, output rise/ falltime, output skew. • Programmable spread percentage for EMI control. • Watchdog timer technology to reset system if system malfunctions. • Programmable watch dog safe frequency. • Support I2C Index read/write and block read/write operations. • Supports spread spectrum for EMI reduction; default is spread spectrum ON.
Pin Configuration
VDDREF FS0/REF0 FS1/REF1 FS2/REF2 GNDREF X1 X2 GND VDD *VttPWR_GD/PD# PCI66/33#_SEL PCI_STOP#* VDDPCI FS3/PCICLK_F0 FS4/PCICLK_F1 PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 GNDPCI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDSDR SDRAM_OUT GNDSDR CPU_STOP#* CPUCLKT1 CPUCLKC1 VDDCPU GNDCPU CPUCLKT0 CPUCLKC0 IREF GND AVDD SCLK SDATA GNDAGP AGPCLK0 AGPCLK1 VDDAGP AVDD48 48MHz_0 48MHz_1 24_48MHz/SEL24_48#MHz** GND48
48-Pin TSSOP & SSOP
* These inputs have a 120K pull up to VDD. ** These inputs have a 120K pull down to GND.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz (0:1) 24_48MHz
Skew Requirements
PCI-PCI AGP-AGP CPU-AGP CPU-PCI
3
ICS951402
<±350ps <±350ps <±500ps <±500ps <±1ns <±1ns
REF (2:0)
CPU DIVDER
Stop
2 2
CPUCLKT (1:0) CPUCLKC (1:0)
AGP-PCI AGP leading CPU-SDRAM
SDATA SCLK FS (4:0) PD# PCI_STOP# CPU_STOP# PD#/Vtt_PWRGD PCI66/33#SEL 24_48SEL#
SDRAM
Control Logic
PCI DIVDER Stop
1
SDRAM_OUT
Power Groups
6
PCICLK (5:0) PCICLK_F (1:0)
Config. Reg.
2
AGP DIVDER
2
AGP (1:0) I REF
VDDCPU = CPU VDDPCI = PCICLK_F, PCICLK VDDSD = SDRAM AVDD48 = 48MHz, 24MHz, fixed PLL AVDD = Analog Core PLL VDDAGP= AGP VDDREF = Xtal, REF
0660—05/05/05 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
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ICS951402 Advance Information
Pin Description
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 PIN NAME VDDREF FS0/REF0 FS1/REF1 FS2/REF2 GNDREF X1 X2 GND VDD *VttPWR_GD/PD# TYPE PWR I/O I/O I/O PWR IN OUT PWR PWR IN DESCRIPTION Ref, XTAL power supply, nominal 3.3V Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Ground pin for the REF outputs. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Power supply, nominal 3.3V This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the device into a low power state. Selects all PCI clock frequencies to be 33Mhz or 66Mhz. 0 = 33Mhz , 1 = 66Mhz Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low Power supply for PCI clocks, nominal 3.3V Frequency select latch input pin / 3.3V PCI free running clock output. Frequency select latch input pin / 3.3V PCI free running clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Power supply for PCI clocks, nominal 3.3V PCI clock output. PCI clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Ground pin for the 48MHz outputs 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. 48MHz clock output. 48MHz clock output. Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V Power supply for AGP clocks, nominal 3.3V AGP clock output AGP clock output Ground pin for the AGP outputs Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. 3.3V Analog Power pin for Core PLL Ground pin. This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Complementary clock of differential pair CPU outputs. This clock is 180 degrees out of phase with the SDRAM clock. True clock of differential pair CPU outputs. This clock is in phase with the SDRAM clock Ground pin for the CPU outputs Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. This clock is 180 degrees out of phase with the SDRAM clock. True clock of differential pair CPU outputs. This clock is in phase with the SDRAM clock Stops all CPUCLK besides the free running clocks Ground pin for the SDRAM outputs. SDRAM seed clock output for external buffer Supply for SDRAM clocks, nominal 3.3V.
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
PCI66/33#_SEL PCI_STOP#* VDDPCI FS3/PCICLK_F0 FS4/PCICLK_F1 PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 GNDPCI GND48 24_48MHz/SEL24_48#MHz** 48MHz_1 48MHz_0 AVDD48 VDDAGP AGPCLK1 AGPCLK0 GNDAGP SDATA SCLK AVDD GND IREF
IN IN PWR I/O I/O OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR I/O OUT OUT PWR PWR OUT OUT PWR I/O IN PWR PWR OUT
39 40 41 42 43 44 45 46 47 48
0660—05/05/05
CPUCLKC0 CPUCLKT0 GNDCPU VDDCPU CPUCLKC1 CPUCLKT1 CPU_STOP#* GNDSDR SDRAM_OUT VDDSDR
OUT OUT PWR PWR OUT OUT IN PWR OUT PWR
2
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ICS951402 Advance Information
Table 1: Clock Power Management Truth Table
Byte 6 Bit 6 Byte 6 Bit 7 PD# CPU_ STOP Stoppable CPU (Not free-run) Non-stop CPU (Free-run) Note
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
IREF x 2 IREF x 2 IREF x 6 RUN Hi Z Hi Z Hi Z RUN Hi Z Hi Z IREFx6 RUN Hi Z Hi Z HI Z RUN
IREF x 2 IREF x 2 RUN RUN IREF x 2 IREF x 2 RUN RUN Hi Z Hi Z RUN RUN Hi Z Hi Z RUN RUN
Non Tri-state Mode CPU_stop# Tri-state Mode PD# & Tri-state Mode PD# & CPU_stop# Tri-state Mode
0660—05/05/05
3
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ICS951402 Advance Information
General I2C serial interface information for the ICS951402 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • •
How to Read:
• • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit Slave Address D2(H) WR WRite T Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
0660—05/05/05
4
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ICS951402 Advance Information
Serial Configuration Command Bitmap
CPU MHz FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 100.00 133.34 200.01 166.65 100.00 133.34 133.16 166.45 105.00 140.00 66.67 175.00 109.99 146.65 210.00 183.27 99.51 132.68 199.02 165.85 99.51 132.68 132.59 165.73 99.39 132.51 198.77 165.64 99.39 132.51 132.36 165.45 SDRAM MHz 100.00 133.34 200.01 166.65 133.34 100.00 166.45 133.16 105.00 140.00 66.67 175.00 109.99 146.65 210.00 183.27 99.51 132.68 199.02 165.85 132.68 99.51 165.73 132.59 99.39 132.51 198.77 165.64 132.51 99.39 165.45 132.36 3V66 MHz PCI MHz REF MHz USB/DOT MHz 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 48.008 With Spread Enabled…
66.67 66.67 66.67 66.66 66.67 66.67 66.58 66.58 70.00 70.00 66.67 70.00 73.33 73.33 70.00 73.31 66.34 66.34 66.34 66.34 66.34 66.34 66.29 66.29 66.26 66.26 66.26 66.25 66.26 66.26 66.18 66.18
33.33 33.33 33.33 33.33 33.33 33.33 33.29 33.29 35.00 35.00 33.33 35.00 36.
