CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER

www.DataSheet4U.com PRELIMINARY FEMTOCLOCKS™ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER ICS8422002I-01 Features • • • • • • • • Two LVHSTL outputs (VOHmax = 1.2V) Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz VCO range: 560MHz - 680MHz RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical) Power supply modes: Core/Output 3.3V/1.8V 2.5V/1.8V -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages General Description The ICS8422002I-01 is a 2 output LVHSTL Synthesizer optimized to generate Ethernet HiPerClockS™ reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The ICS8422002I-01 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS8422002I-01 is packaged in a small 20-pin TSSOP package. ICS Pin Assignment nc VDDO Q0 nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDO Q1 nQ1 GND VDD nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1 Block Diagram F_SEL[1:0] Pulldown nPLL_SEL Pulldown 2 ICS422002I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Q0 1 F_SEL[1:0] 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 Not Used nQ0 REF_CLK Pulldown 25MHz 1 XTAL_IN OSC XTAL_OUT nXTAL_SEL Pulldown 0 Phase Detector VCO Q1 nQ1 0 M = 25 (fixed) MR Pulldown The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 1 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 www.DataSheet4U.com ICS8422002I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Table 1. Pin Descriptions Number 1, 7 2, 20 3, 4 Name nc VDDO Q0, nQ0 Power Output Type Unused Description No connect. Output supply pins. Differential output pair. LVHSTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and REF_CLK as input to the dividers. When LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pins. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. Selects between crystal or REF_CLK inputs as the PLL Reference source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. Power supply ground. Differential output pair. LVHSTL interface levels. 5 MR Input Pulldown 6 8 9, 11 10, 16 12, 13 14 15 17 18, 19 nPLL_SEL VDDA F_SEL0, F_SEL1 VDD XTAL_OUT, XTAL_IN REF_CLK nXTAL_SEL GND nQ1, Q1 Input Power Input Power Input Input Input Power Output Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF kΩ IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 2 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 www.DataSheet4U.com ICS8422002I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 50mA 100mA 73.2°C/W (0 lfpm) -65°C to 150°C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 1.6 Typical 3.3 3.3 1.8 90 10 0 Maximum 3.465 3.465 2.0 Units V V V mA mA mA Table 3B. Power Supply DC Characteristics, VDD = VDDA = 2.5V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 1.6 Typical 2.5 2.5 1.8 80 10 0 Maximum 2.625 2.625 2.0 Units V V V mA mA mA IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 3 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 w w w . D a t a S h e e t 4 U . c o m ICS8422002I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Table 3C. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C Symbol VIH Parameter Input High Voltage Test Conditions VDD = 3.3V VDD = 2.5V Input Low Voltage Input High Current Input Low Current REF_CLK, MR, F_SEL[0:1], nPLL_SEL, nXTAL_SEL REF_CLK, MR, F_SEL[0:1], nPLL_SEL, nXTAL_SEL VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -5 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 Units V V V V µA µA VIL IIH IIL Table 3D. LVHSTL DC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C Symbol VOH VOL VOX VSWING Parameter Output High Current; NOTE 1 Output Low Current; NOTE 1 Output Crossover Voltage; NOTE 2 Peak-to-Peak Output Voltage Swing Test Conditions Minimum 1.0 0 40 0.6 Typical Maximum 1.2 0.4 60 1.1 Units V V % V NOTE 1: Outputs termination with 50Ω to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. Table 3E. LVHSTL DC Characteristics, VDD = VDDA = 2.5V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C Symbol VOH VOL VOX VSWING Parameter Output High Current; NOTE 1 Output Low Current; NOTE 1 Output Crossover Voltage; NOTE 2 Peak-to-Peak Output Voltage Swing 40 0.9 Test Conditions Minimum 1.0 0.235 60 Typical Maximum 1.2 Units V V % V NOTE 1: Outputs termination with 50Ω to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. Table 4. Crystal Characteristics Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 22.4 Test Conditions Minimum Typical Fundamental 25 27.2 50 7 1 MHz Maximum Units Ω pF mW IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 4 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 www.DataSheet4U.com ICS8422002I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C Parameter fOUT tsk(o) tjit() tR / tF odc Symbol Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz – 20MHz) RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Duty Cycle 125MHz, (1.875MHz – 20MHz) 62.5MHz, (1.875MHz – 20MHz) 20% to 80% Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 Minimum 140 112 56 TBD 0.44 0.48 0.49 410 50 Typical Maximum 170 136 68 Units MHz MHz MHz ps ps ps ps ps % NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Table 5B. AC Characteristics, VDD = VDDA = 2.5V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C Parameter fOUT tsk(o) tjit() tR / tF odc Symbol Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz – 20MHz) RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Duty Cycle 125MHz, (1.875MHz – 20MHz) 62.5MHz, (1.875MHz – 20MHz) 20% to 80% Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 Minimum 140 112 56 TBD 0.41 0.49 0.50 380 50 Typical Maximum 170 136 68 Units MHz MHz MHz ps ps ps ps ps % NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 5 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 www.DataSheet4U.com ICS8422002I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Typical Phase Noise at 156.25MHz -10 -20 -30 -40 -50 dBc Hz -60 -70 -80 -90 -100 -110 -120 -130 -140 -160 -170 -180 -190 100 -150 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) ➝ Ethernet Filter 100k 0 Noise Power 1k 10k ➝ Offset Frequency (Hz) ➝ Raw Phase Noise Data Phase Noise Result by adding an Ethernet filter to raw data 1M 10M 100M IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 6 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 www.DataSheet4U.com ICS8422002I-01 FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY Parameter Measurement Informat