41/2 Digit LCD/ Single-Chip A/D Converter

ICL7129 August 1997 41/2 Digit LCD, Single-Chip A/D Converter Description The Intersil ICL7129 is a very high performance 41/2-digit, analog-to-digital converter that directly drives a multiplexed liquid crystal display. This single chip CMOS integrated circuit requires only a few passive components and a reference to operate. It is ideal for high resolution hand-held digital multimeter applications. The performance of the ICL7129 has not been equaled before in a single chip A/D converter. The successive integration technique used in the ICL7129 results in accuracy better than 0.005% of full scale and resolution down to 10µV/count. The ICL7129, drawing only 1mA from a 9V battery, is well suited for battery powered instruments. Provision has been made for the detection and indication of a “LOW/BATTERY” condition. Autoranging instruments can be made with the ICL7129 which provides overrange and underrange outputs and 10:1 range changing input. The ICL7129 instantly checks for continuity, giving both a visual indication and a logic level output which can enable an external audible transducer. These features and the high performance of the ICL7129 make it an extremely versatile and accurate instrument-on-a-chip. Features • • • • • • • • • • ±19,999 Count A/D Converter Accurate to ±4 Count 10µV Resolution on 200mV Scale 110dB CMRR Direct LCD Display Drive True Differential Input and Reference Low Power Consumption Decimal Point Drive Outputs Overrange and Underrange Outputs Low Battery Detection and Indication 10:1 Range Change Input Ordering Information PART NUMBER ICL7129CPL ICL7129RCPL ICL7129CM44 TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 PACKAGE 40 Ld PDIP 40 Ld PDIP 44 Ld MQFP PKG. NO. E40.6 E40.6 Q44.10x10 NOTE: “R” indicates device with reversed leads. Pinouts ICL7129 (PDIP) TOP VIEW OSC1 1 OSC3 2 ANNUNCIATOR 3 DRIVE B1 , C1 , CONT 4 A1 , G1 , D1 5 F1 , E1 , DP1 6 DISPLAY OUTPUT LINES B2 , C2 , LO BAT 7 A2 , G2 , D2 8 F2 , E2 , DP2 9 B3 , C3 , MINUS 10 A3 , G3 , D3 11 F3 , E3 , DP3 12 B4 , C4 , BC5 13 A4 , D4 , G4 14 F4 , E4 , DP4 15 BP3 16 BP2 17 BP1 18 VDISP 19 DP4 /OR 20 40 OSC2 39 DP1 38 DP2 37 RANGE 36 DGND 35 REF LO 34 REF HI 33 IN HI 32 IN LO 31 BUFF 30 CREF29 CREF+ 28 COMMON 27 CONTINUITY 26 INT OUT 25 INT IN 24 V+ 23 V22 LATCH/HOLD B2 , C2 , LO BAT B3 , C3 , MINUS A1 , G1 , D1 F1 , E1 , DP1 A2 , G2 , D2 F2 , E2 , DP2 A3 , G3 , D3 F3 , E3 , DP3 B4 , C4 , BC5 A4 , D4 , G4 21 DP3 /UR F4 , E4 , DP4 DGND RANGE DP2 DP1 OSC 2 OSC 1 OSC 3 NC NC ANNUNCE DRIVE B1 , C1 , CONT 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 31 30 29 28 27 26 25 V+ VNC NC LATCH/ HOLD DP3 /UR DP4 /OR VDISP BP1 BP2 BP3 ICL7129 (MQFP) TOP VIEW CONTINUITY COMMON INT OUT REF LO REF HI CREF+ CREF- 24 10 11 23 12 13 14 15 16 17 18 19 20 21 22 INT IN BUFF IN LO IN HI CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 3085.1 3-31 ICL7129 Functional Block Diagram LOW BATTERY CONTINUITY SEGMENT DRIVES BACKPLANE DRIVES ANNUNCIATOR DRIVE LATCH, DECODE DISPLAY MULTIPLEXER OSC1 VDISP OSC2 UP/DOWN RESULTS COUNTER OSC3 SEQUENCE COUNTER/DECODER CONTROL LOGIC ANALOG SECTION RANGE L/H CONT V+ V- DGND OR DP3 UR DP3 DP2 DP1 Typical Application Schematic LOW BATTERY CONTINUITY V+ 5pF (MICA) 20 21 19 22 18 23 17 24 + 16 15 26 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ICL7129 120kHz 9V 25 560pF 10pF (MICA) 1.2kΩ 0.1µF 150kΩ 10kΩ 1.0µF 0.1µF ICL8069 + 27 28 29 30 31 32 33 + 100kΩ 34 35 20K 36 37 38 39 40 270K V+ 6.8µF - - VIN 3-32 ICL7129 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Reference Voltage (REF HI or REF LO). . . . . . . . . . . . . . . . V+ to VInput Voltage (Note 1), IN HI or IN LO . . . . . . . . . . . . . . . . . V+ to VVDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND -0.3V to V+ Digital Input Pins 1, 2, 19, 20, 21, 22, 27, 37, 38, 39, 40 . . . . . . . . . . . . . DGND to V+ Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltages provided that input current is limited to 1400mA. Currents above this value may result in valid display readings but will not destroy the device if limited to ±1mA. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Zero Input Reading Zero Reading Drift Ratiometric Reading Range Change Accuracy Rollover Error Linearity Error V- to V+ = 9V, VREF = 1.00V, TA = 25oC, fCLK = 120kHz, Unless Otherwise Specified TEST CONDITIONS VIN = 0V, 200mV Scale VIN = 0V, 0oC To 70oC VIN = VREF = 1000mV, RANGE = 2V VIN = 0.10000V on Low, Range ≈ VIN = 1.0000V on High Range -VIN = +VIN = 199mV 200mV Scale VCM = 1V,VIN = 0V, 200mV Scale VIN = 0V, 200mV Scale MIN -0000 9996 0.9999 2.8 4.5 6 6.3 100 TYP 0000 ±0.5 9999 1.0000 1.5 1.0 110 (V-) +1.5 (V+) -1.0 14 1 2 3.2 0.6 10 5.3 1.2 9 1.0 120 50 7.2 200 200 2 3/3 3/9 40 3 MAX +0000 10000 1.0001 3.0 10 7 3.5 5.8 12 1.5 360 7.7 400 10 UNITS Counts µV/oC Counts Ratio Counts Counts dB V µV pA ppm/oC V mA µA V mA V mA kHz kΩ V mV mV µA µA µA µA µA Input Common-Mode Rejection Ratio Input Common-Mode Voltage Range Noise (Peak-To-Peak Value not Exceeded 95% of Time) VIN = 0V 200mV Scale Input Leakage Current Scale Factor Tempco COMMON Voltage COMMON Sink Current COMMON Source Current DGND VoItage DGND Sink Current Supply Voltage Range Supply Current Excluding COMMON Current Clock Frequency VDISP Resistance Low Battery Flag Activation Voltage CONTINUITY Comparator Threshold Voltages VIN = 0V, Pin 32, 33 VIN = 199mV 0oC To 70oC External VREF = 0ppm/oC V+ to Pin 28 ∆Common = + 0.1V ∆Common = -0.1V V+ to Pin 36, V+ to V- = 9V ∆DGND = +0.5V V+ to V- (Note 3) V+ to V- = 9V (Note 3) VDISP to V+ V+ to VVOUT Pin 27 = HI VOUT Pin 27 = LO Pull-Down Current “Weak Output” Current Sink/Source Pins 37, 38, 39 Pins 20, 21 Sink/Source Pin 27 Sink/Source Pin 22 Source Current Pin 22 Sink Current NOTE: 3. Device functionality is guaranteed at the stated Min/Max limits. However, accuracy can degrade under these conditions. 3-33 ICL7129 Pin Descriptions PIN 1 2 3 SYMBOL OSC1 OSC3 ANNUNCIATOR DRIVE B1 , C1 , CONT A1 , G1 , D1 F1 , E1 , DP1 DESCRIPTION Input to first clock inverter. Output of second clock inverter. Backplane squarewave output for driving annunciators. Output to display segments. Output to display segments. Output to display segments. PIN 23 24 SYMBOL VV+ DESCRIPTION Negative power supply terminal. Positive power supply terminal, and positive rail for display drivers. Input to integrator amplifier. Output of integrator amplifier. INPUT: When LO, continuity flag on the display is off. When HI, continuity flag is on. OUTPUT: HI when voltage between inputs is less than +200mV. LO when voltage between inputs is more than +200mV. 28 COMMON Sets common-mode voltage of 3.2V below V+ for DE, 10X, etc., Can be used as pre-regulator for external reference. Positive side of external reference capacitor. Negative side of external reference capacitor. Output of buffer amplifier. Negative input voltage terminal. Positive input voltage terminal. Positive reference voltage input terminal. Negative reference voltage input terminal. Ground reference for digital section. 3µA pull-down for 200mV scale. Pulled HIGH externally for 2V scale. Internal 3µA pull-down. When HI, decimal point 2 will be on. Internal 3µA pull-down. When HI, decimal point 1 will be on. Output of first clock inverter. Input of second clock inverter. 25 26 27 INT IN INT OUT CONTINUITY 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 B2 , C2 , LO BATT Output to display segments. A2 , G2 , D2 F2 , E2 , DP2 B3 , C3 , MINUS A3 , G3 , D3 F3 , E3 , DP3 B4 , C4 , BC5 A4 , D4 , G4 F4 , E4 , DP4 BP3 BP2 BP1 VDlSP DP4 /OR Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Backplane #3 output to display. Backplane #2 output to display. Backplane #1 output to display. Negative rail for display drivers. INPUT: When HI, turns on most significant decimal point. OUTPUT: Pulled HI when result count exceeds ±19,999. 31 32 33 34 BUFFER IN LO IN HI REF HI 29 CREF+ 30 CREF- 35 REF LO 36 37 DGND RANGE 21 DP3 /UR INPUT: Second most significant decimal point on when HI. OUTPUT: Pulled HI when result count is less than ±1,000. 38 DP2 39 DP1 22 LATCH/HOLD INPUT: When floating, A/D converter operates in the free-run mode. When pulled HI, the last displayed reading is held. When pulled LO, the result counter contents are shown incrementing during the de-integrate phase of cycle. OUTPUT: Negative going edge occurs when the data latches are updated. Can be used for converter status signal. 40 OSC2 3-34 ICL7129 Detailed Description The ICL7129 is a uniquely designed single chip A/D converter. It features a new “successive integration” technique to achieve 10µV resolution