184Pin Unbuffered DDR SDRAM DIMMs

www.DataSheet4U.com 184pin Unbuffered DDR SDRAM DIMMs based on 512Mb C ver. (TSOP) This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 512Mb C ver. DDR SDRAMs in 400mil TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb C ver. based unbuffered DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • • • • • • • JEDEC Standard 184-pin dual in-line memory module (DIMM) Two ranks 128M x 72, 128M x 64 and One rank 64M x 72, 64M x 64, 32M x 64 organization 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400, 2.5V ± 0.2V for DDR333 and below All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 133/166/200MHz DLL aligns DQ and DQS transition with CK transition Programmable CAS Latency: DDR266(2, 2.5 clock), DDR333(2.5 clock), DDR400(3 clock) • • • • • • • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Edge-aligned DQS with data outs and Center-aligned DQS with data inputs Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial Presence Detect (SPD) with EEPROM Built with 512Mb DDR SDRAMs in 400 mil TSOP II packages All lead-free products (RoHS compliant) ADDRESS TABLE Organization 256MB 512MB 512MB 1GB 1GB 32M x 64 64M x 64 64M x 72 128M x 64 128M x 72 Ranks 1 1 1 2 2 SDRAMs 32Mb x 16 64Mb x 8 64Mb x 8 64Mb x 8 64Mb x 8 DataSheet4U.com # of DRAMs 4 8 9 16 18 # of row/bank/column Address 13(A0~A12)/2(BA0,BA1)/10(A0~A9) 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms DataShee PERFORMANCE RANGE Part-Number Suffix Speed Bin CL - tRCD- tRP CL=3 Max Clock Frequency CL=2.5 CL=2 -D431 DDR400B 3-3-3 200 166 133 -J DDR333 2.5-3-3 166 133 -H DDR266B 2.5-3-3 133 133 Unit CK MHz MHz MHz Note: 1. 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ± 0.2V for DDR333 and below This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Nov. 2005 1 DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com 11 184pin Unbuffered DDR SDRAM DIMMs ORDERING INFORMATION Part Number HYMD532646CP6-H HYMD532646CP6J-D43/J HYMD564646CP8-H HYMD564646CP8J-D43/J HYMD564726CP8-H HYMD564726CP8J-D43/J HYMD512646CP8-H HYMD512646CP8J-D43/J HYMD512726CP8-H HYMD512726CP8J-D43/J Density Organization 256MB 256MB 512MB 512MB 512MB 512MB 1GB 1GB 1GB 1GB 32Mb x 16 32Mb x 16 64Mb x 8 64Mb x 8 64Mb x 8 64Mb x 8 64Mb x 8 64Mb x 8 64Mb x 8 64Mb x 8 # of DRAMs 4 4 8 8 9 9 16 16 18 18 Material Lead-free1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ DIMM Dimension 133.35 x 31.75 x 3.18 [mm3] ↑ ↑ ↑ ↑ ↑ 133.35 x 31.75 x 4 [mm3] ↑ ↑ ↑ ECC Support None None None None ECC ECC None None ECC ECC Note: 1. The “Lead-free” products contain Lead less than 0.1% by weight and satisfy RoHS - please contact Hynix for product availability. * These products are built with HY5DU124(8,16)22CTP, the Hynix DDR SDRAM component. et4U.com DataSheet4U.com DataShee Rev. 1.2 / Nov. 2005 2 DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com 11 184pin Unbuffered DDR SDRAM DIMMs PIN DESCRIPTION Pin CK0, /CK0 CS0, CS1 CKE0, CKE1 /RAS, /CAS, /WE A0 ~ A12 BA0, BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS17 DM0~7 VDD /RESET Pin Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply Reset Enable VDDQ VSS VREF VDDSPD SA0~SA2 SCL SDA WP VDDID DU NC FETEN Pin Pin Description DQs Power Supply Ground Reference Power Supply Power Supply for SPD E2PROM Address Inputs E2PROM Clock E2PROM Data I/O Write Protect Flag VDD Identification Flag Do not Use No Connection FET Enable PIN ASSIGNMENT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ CK1* /CK1* VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Name A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0/NC CB1/NC VDD DQS8 A0 CB2/NC VSS CB3/NC BA1 Key DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Name Pin Name VDDQ 93 VSS /WE 94 DQ4 DQ41 95 DQ5 /CAS 96 VDDQ VSS 97 DM0,DQS9 DQS5 98 DQ6 DQ42 99 DQ7 DQ43 100 VSS VDD 101 NC /CS2* 102 NC DataSheet4U.com DQ48 103 NC DQ49 104 VDDQ VSS 105 DQ12 CK2* 106 DQ13 /CK2* 107 DM1,DQS10 VDDQ 108 VDD DQS6 109 DQ14 DQ50 110 DQ15 DQ51 111 CKE1 VSS 112 VDDQ VDDID 113 BA2* DQ56 114 DQ20 DQ57 115 A12 VDD 116 VSS DQS7 117 DQ21 DQ58 118 A11 DQ59 119 DM2,DQS11 VSS 120 VDD NU 121 DQ22 SDA 122 A8 SCL 123 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Name VSS A6 DQ28 DQ29 VDDQ DM3,DQS12 A3 DQ30 VSS DQ31 CB4/NC CB5/NC VDDQ CK0 /CK0 VSS DM8,DQS17 A10 CB6/NC VDDQ CB7/NC key VSS DQ36 DQ37 VDD DM4,DQS13 DQ38 DQ39 VSS DQ44 Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Name /RAS DQ45 VDDQ /CS0 /CS1 DM5,DQS14 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 A132, NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7,DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD et4U.com DataShee Note: 1. * : These pins are not used in this module. 2. Pin 167 is NC for 256MB, 512MB, and 1GB, or A13 for 2GB module. Rev. 1.2 / Nov. 2005 3 DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com 11 184pin Unbuffered DDR SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 256MB, 32M x 64 Unbuffered DIMM: HYMD532646CP6[J] /CS0 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS LDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 /CS D0 DQS5 DM5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS4 DM4/DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQS LDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 /CS D2 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 et4U.com DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQS LDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 /CS DQS7 DM7/DQS16 D1 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS6 DataSheet4U.com DM6/DQS15 LDQS LDM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 UDQS UDM I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 /CS D3 DataShee I/O15 I/O15 Serial PD SCL W P A0 SDA A1 A2 *Clock Wiring SDRAMs Clock Input VDD SPD VDD /VDDQ VREF VSS VDDID SPD DO-D3 DO-D3 DO-D3 SA0 SA1 SA2 *CK0, /CK0 *CK1, /CK1 *CK2, /CK2 NC 2 SDRAMs 2 SDRAMs *Wire per Clock Loading Table/Wiring Diagrams Strap:see Note 4 Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors : 22 Ohms +- 5%. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN) : VDD = VDDQ STRAP IN (VSS) : VDD ≠ V DDQ 5. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms +- 5% BA0-BA1 A0-A13 /RAS /CAS CKE0 /WE BA0-BA1 : SDRAMs D0-D3 A0-A13 : SDRAMs D0-D3 /RAS : SDRAMs D0-D3 /CAS : SDRAMs D0-D3 CKE : SDRAMs D0-D3 /WE : SDRAMs D0-D3 Rev. 1.2 / Nov. 2005 4 DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com 11 184pin Unbuffered DDR SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB, 64M x 64 Unbuffered DIMM: HYMD564646CP8[J] /CS0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Serial PD SCL SDA W P A0 A1 A2 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS DQS4 DM4/DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6/DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS D0 D4 D1 D5 D2 DataSheet4U.com D6 et4U.com DataShee DQS7 DM7/DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VDD SPD VDD /VDDQ VREF VSS VDDID Notes : SPD DO-D7 DO-D7 DO-D7 Strap:see Note 4 D3 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 /CS DQS D7 *Clock Wiring Clock Input *CK0, /CK0 *CK1, /CK1 *CK2, /CK2 SDRAMs 2 SDRAMs 3 SDRAMs 3 SDRAMs SA0 SA1 SA2 *Wire per Clock Loading Table/Wiring Diagrams BA0-BA1 A0-A13 /RAS /CAS CKE0 /WE BA0-BA1 : SDRAMs D0-D7 A0-A13 : SDRAMs D0-D7 /RAS : SDRAMs D0-D7 /CAS : SDRAMs D0-D7 CKE : SDRAMs D0-D7 /WE : SDRAMs D0-D7 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors : 22 Ohms +- 5%. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN) : VDD = VDDQ STRAP IN (VSS) : VDD ≠ V DDQ 5. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms +- 5% Rev. 1.2 / Nov. 2005 5 DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com 11 184pin Unbuffered DDR SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB, 64M x 72 ECC Unbuffered DIMM : HYMD564726CP8[J] /CS0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 D