PC100 SDRAM Unbuffered DIMM

www.DataSheet4U.com 16Mx64bits PC100 SDRAM Unbuffered DIMM based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh HYM71V16655BT8 Series DESCRIPTION Preliminary The Hynix HYM71V16655BT8 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB. The Hynix HYM71V16655BT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The Hynix HYM71V16655BT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. FEATURES • • • • PC100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.15” (29.21mm) Height PCB with single sided components Single 3.3±0.3V power supply - 1, 2, 4 or 8 or Full page for Sequential Burst • • All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Interleave Burst Data mask function by DQM • Programmable CAS Latency ; 2, 3 Clocks • • • • • • SDRAM internal banks : four banks Module bank : one physical bank Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type ORDERING INFORMATION Part No. HYM71V16655BT8-8 HYM71V16655BT8-P HYM71V16655BT8-S Clock Frequency 125MHz 100MHz 100MHz Internal Bank Ref. Power SDRAM Package Plating 4 Banks 4K Normal TSOP-II Gold This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Nov. 01 2 www.DataSheet4U.com PC100 SDRAM Unbuffered DIMM HYM71V16655BT8 Series PIN DESCRIPTION PIN CK0~CK3 CKE0 /S0, /S2 BA0, BA1 A0 ~ A11 /RAS, /CAS, /WE DQM0~DQM7 DQ0 ~ DQ63 VCC VSS SCL SDA SA0~2 WP NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect for Serial Presence Detect on DIMM No connection Rev. 0.1/Nov. 01 3 www.DataSheet4U.com PC100 SDRAM Unbuffered DIMM HYM71V16655BT8 Series PIN ASSIGNMENTS FRONT SIDE PIN NO. 1 2 3 4 5 6 7 8 9 10 BACK SIDE PIN NO. 85 86 87 88 89 90 91 92 93 94 FRONT SIDE PIN NO. 41 42 43 44 45 46 47 48 49 50 51 52 BACK SIDE PIN NO. 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 NAME VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NAME VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 NAME VCC CK0 VSS NC /S2 DQM2 DQM3 NC VCC NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VCC NAME *CK1 NC VSS CKE0 NC DQM6 DQM7 NC VCC NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS *CK3 NC SA0 SA1 SA2 VCC Architecture Key 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC NC VSS NC NC VCC /WE DQM0 DQM1 /S0 NC VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 Voltage Key DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC NC VSS NC NC VCC /CAS DQM4 DQM5 NC /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Note : * CK1 and CK3 are connected with termination R/C (Refer to the block diagram) Rev. 0.1/Nov. 01 4 www.DataSheet4U.com PC100 SDRAM Unbuffered DIMM HYM71V16655BT8 Series BLOCK DIAGRAM Note : 1. The serial resistor values of DQs are 10ohms 2. The padding capacitance of termination R/C for CK1,CK3 is 10pF Rev. 0.1/Nov. 01 5 www.DataSheet4U.com PC100 SDRAM Unbuffered DIMM HYM71V16655BT8 Series SERIAL PRESENCE DETECT BYTE NUMBER BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 BYTE10 BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 BYTE22 BYTE23 BYTE24 BYTE25 BYTE26 BYTE27 BYTE28 BYTE29 BYTE30 BYTE31 BYTE32 BYTE33 BYTE34 BYTE35 BYTE36 ~61 BYTE62 BYTE63 BYTE64 BYTE65 ~71 FUNCTION DESCRIPTION # of Bytes Written into Serial Memory at Module Manufacturer Total # of Bytes of SPD Memory Device Fundamental Memory Type # of Row Addresses on This Assembly # of Column Addresses on This Assembly # of Module Banks on This Assembly Data Width of This Assembly Data Width of This Assembly (Continued) Voltage Interface Standard of This Assembly SDRAM Cycle Time @/CAS Latency=3 Access Time from Clock @/CAS Latency=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back to Back Random Column Address Burst Lenth Supported # of Banks on Each SDRAM Device SDRAM Device Attributes, /CAS Lataency SDRAM Device Attributes, /CS Lataency SDRAM Device Attributes, /WE Lataency SDRAM Module Attributes SDRAM Device Attributes, General SDRAM Cycle Time @/CAS Latency=2 Access Time from Clock @/CAS Latency=2 SDRAM Cycle Time @/CAS Latency=1 Access Time from Clock @/CAS Latency=1 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active Delay (tRRD) Minimum /RAS to /CAS Delay (tRCD) Minimum /RAS Pulse Width (tRAS) Module Bank Density Command and Address Signal Input Setup Time Command and Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information (may be used in future) SPD Revision Checksum for Byte 0~62 Manufacturer JEDEC ID Code ....Manufacturer JEDEC ID Code 2ns 1ns 2ns 1ns 8ns 6ns FUNCTION VALUE -8 -P 128 Bytes 256 Bytes SDRAM 12 10 1 Bank 64 Bits LVTTL 10ns 6ns None 15.625us / Self Refresh Supported x8 None tCCD = 1 CLK 1,2,4,8,Full Page 4 Banks /CAS Latency=2,3 /CS Latency=0 /WE Latency=0 -S -8 -P 80h 08h 04h 0Ch 0Ah 01h 40h 00h 01h -S NOTE 1 10ns 6ns 80h 60h A0h 60h 00h 80h 08h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh A0h 60h 2 Neither Buffered nor Registered +/- 10% voltage tolerence, Burst Read Single Bit Write, Precharge All, Auto Precharge, Early RAS Precharge 8ns 6ns 20ns 16ns 20ns 48ns 10ns 6ns 20ns 20ns 20ns 50ns 128MB 2ns 1ns 2ns 1ns Intel SPD 1.2B Hynix JEDED ID Unused HSI (Korea Area) HSA (United States Area) HSE (Europe Area) HSJ (Japan Area) HSS(Singapore) ASIA Area F0h 2ns 1ns 2ns 1ns 20h 10h 20h 10h 12ns 6ns 20ns 20ns 20ns 50ns A0h 60h 00h 00h 14h 10h 14h 30h A0h 60h 00h 00h 14h 14h 14h 32h 20h 20h 10h 20h 10h 00h 12h 16h ADh FFh 0*h 1*h 2*h 3*h 4*h 5*h C0h 60h 00h 00h 14h 14h 14h 32h 20h 10h 20h 10h 3, 8 36h BYTE72 Manufacturing Location 10 Rev. 0.1/Nov. 01 6 www.DataSheet4U.com PC100 SDRAM Unbuffered DIMM HYM71V16655BT8 Series Continued BYTE NUMBER BYTE73 BYTE74 BYTE75 BYTE76 BYTE77 BYTE78 BYTE79 BYTE80 BYTE81 BYTE82 BYTE83 BYTE84 BYTE85 BYTE86 ~90 BYTE91 BYTE92 BYTE93 BYTE94 BYTE95 ~98 BYTE99 ~125 BYTE126 BYTE127 BYTE128 ~256 FUNCTION DESCRIPTION Manufacturer’s Part Number (Component) Manufacturer’s Part Number (128Mb based) Manufacturer’s Part Number (Voltage Interface) Manufacturer’s Part Number (Memory Width) ....Manufacturer’s Part Number (Memory Width) Manufacturer’s Part Number (Data Width) ....Manufacturer’s Part Number (Data Width) Manufacturer’s Part Number (Refresh, SDRAM Bank) Manufacturer’s Part Number (Generation) Manufacturer’s Part Number (Package Type) Manufacturer’s Part Number (Component Configuration) Manufacturer’s Part Number (Hyphent) Manufacturer’s Part Number (Min. Cycle Time) Manufacturer’s Part Number Revision Code (for Component) ....Revision Code (for PCB) Manufacturing Date ....Manufacturing Date Assembly Serial Number Manufacturer Specific Data (may be used in future) System Frequency Support Intel Specification Details for 100MHz Support Unused Storage Locations FUNCTION -8 -P 7 (SDRAM) 1 V (3.3V, LVTTL) 1 6 6 5 5 (4K Refresh, 4Banks) B T 8 (x8 based) - (Hyphen) VALUE -S -8 -P 37h 31h 56h 31h 36h 36h 35h 35h 42h 54h 38h 2Dh -S NOTE 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 8 P Blanks Process Code Process Code Year Work Week Serial Number None 100MHz Refer to Note7 - S 38h 50h 20h 00h 64h 53h 4, 5 4, 5 4, 6 4, 6 3, 6 3, 6 6 7, 8 AFh AFh 00h ADh 7, 8 Note : 1. The bank address is excluded 2. 1, 2, 4, 8 for Interleave Burst Type 3. BCD adopted 4. ASCII adopted 5. Basically Hynix writes Part No. except for ‘HYM’ in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90 6. Not fixed but dependent 7. CK0, CK2 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge sup