Description
www.DataSheet4U.com HY57V161610D 2 Banks x 512K x 16 Bit Synchronous DRAM D E S C R IP T IO N THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16. HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.) FEATURES • • • Single 3.0V to 3.6V power supply Note1) • • • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequence Burst All device pins are compatible with LVTTL interface JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 and 8 for Interleave Burst • Programmable C A S Latency ; 1, 2, 3 Clocks • • Data mask function by UDQM/LDQM Internal two banks operation O R D E R IN G IN F O R M A T IO N Part No. HY57V161610DTC-5 HY57V161610DTC-55 HY57V161610DTC-6 HY57V161610DTC-7 HY57V161610DTC-8 HY57V161610DTC-10 C lo c k F r e q u e n c y 200MHz 183MHz 166MHz O rganization Interface Package 2Banks x 512Kbits x 16 143MHz 125MHz 100MHz LVTTL 400mil 50pin TSOP II Note : 1. V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied Rev. 3.6/Apr.01 HY57V161610D P IN C O N F IG U R A T IO N VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50pin TSOP-II 400mil x 825mil 0.8mm pin pitch 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS P IN D E S C R IP T IO N PIN P I N N A M E D E S C R IPTIO N The system clock input. All other inputs are referenced to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. Command input enable or mask except CLK, CKE and DQM Select either one of banks during both R A S a n d C A S activity. Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 CLK Clock CKE Clock Enable CS BA Chip Select Bank Address A0 ~ A10 Address Row Address Strobe, RAS, CAS, W E Column Address Strobe, Write Enable LDQM, UDQM DQ0 ~ DQ15 V D D /V S S V D D Q /V S S Q NC Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection R A S , C A S and W E define the operation. Refer function truth table for details DQM control output buffer in read mode and mask input data in write mode Multiplexed data input / output pin Power supply for internal circuit and input buffer Power supply for DQ No connection Rev. 3.6/Apr.01 2 HY57V161610D F U N C T IO N A L B L O C K D IA G R A M 1Mx16 Synchronous DRAM Self Refresh Counter Row Addr. Latch/ Predecoder Refresh Refresh Auto/Self Refresh Interval Timer Counter Row Decoder Address[0:10] R e f . A d d r.[0:11] 512Kx16 Bank 0 Sense AMP & I/O gates Column Decoder DQ0 CLK CKE BA(A11) Data Input/Output Buffers Precharge Row Active Address Register DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 State Machine CS RAS CAS W E UDQM Column Active C o l u m n A d d r. Latch & Counter Overflow Burst Length Counter Column Decoder LDQM Sense AMP & I/O gates Row Addr. Latch/Predecoder 512Kx16 Bank 1 Mode Register Test Mode I/O Control Rev. 3.6/Apr.01 3 HY57V161610D A B S O L U T E M A X IM U M R A T IN G S Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to V SS Voltage on V D D relative to V S S Short Circuit Output Current Power Dissipation S o l d e r i n g T e m p e r a t u r e ·T i m e TA TS T G V IN , V O U T V DD IO S PD TS O L D E R Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 2 6 0 ·1 0 Rating °C °C V V mA W °C · e c S Unit Note : Operation at above absolute maximum rating can adversely affect device reliability. D C O P E R A T IN G C O N D IT IO N Parameter Power Supply Voltage Input high voltage Input low voltage Symbol V DD , V DDQ V IH V IL ( T A = 0 °C t o 7 0 ° C ) Min 3.0 2.0 -0.5 Typ. 3.3 3.0 0 Max 3.6 V DD + 0.3 0.8 Unit V V V Note 1, 2, 3 1, 4 1, 5 Note : 1.All voltages are referenced to V S S = 0V. 2.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 3.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V 4 . V IH ( m a x ) i s a c c e p t a b l e 4 . 6 V A C p u l s e w i d t h w i t h ≤ 1 0 n s o f d u r a t i o n . 5 . V IL ( m i n ) i s a c c e p t a b l e - 1 . 5 V A C p u l s e w i d t h w i t h ≤ 1 0 n s o f d u r a t i o n . A C O P E R A T IN G C O N D IT IO N Parameter AC input high / low level voltage ( T A = 0 °C t o 7 0 ° C , V D D = 3 . 0 V t o 3 . 6 V , V S S = 0 V ) Symbol V IH / V IL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 30 Unit V V ns V pF Note Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement 1 Note : 1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF). For details, refer to AC/DC output load circuit. 2. V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s 3. V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V ‘ Rev. 3.6/Apr.01 4 HY57V161610D C A P A C IT A N C E Parameter CLK Input capacitance A0 ~ A10, BA C K E , C S, R A S , C A S, W E , U D Q M , L D Q M Data input / output capacitance DQ0 ~ DQ15 C I/O 4 6.5 pF ( T A = 2 5 °C , f = 1 M H z ) Pin Symbol CI1 CI2 Min 2.5 2.5 Max 4 5 Unit pF pF O U T P U T L O A D C IR C U IT V t t= 1 . 4 V R T=250 Ω Output Output 3 0p F 3 0p F DC Output Load Circuit AC Output Load Circuit D C C H A R A C T E R IS T IC S I ( T A = 0°C Parameter Power Supply Voltage Input leakage current Output leakage current Output high voltage Output low voltage V DD IL IO VOH VOL Symbol t o 7 0 °C ) Min. 3.0 -1 -1 2.4 - Max 3.6 1 1 0.4 Unit V uA uA V V Note 1, 2 3 4 IO H = - 4 m A IO L = + 4 m A Note : 1.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s . 2.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V 3 . V IN = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t u n d e r t e s t = 0 V 4.D O U T is disabled, V O U T =0 to 3.6V Rev. 3.6/Apr.01 5 HY57V161610D D C C H A R A C T E R IS T IC S II ( T A = 0 ° C t o 7 0 ° C , V D D = 3 . 0 V t o 3 . 6 V , V S S = 0 V Note1,2) Speed Parameter Symbol Test Condition -5 Burst Length=1, One bank active Operating Current ID D 1 tRAS ≥ tRAS(min),tRP ≥ tRP(min), IO=0mA ID D 2 P C K E ≤ VIL(max), tCK = min. C K E ≤ VIL(max), tCK = ∞ C K E ≥ VIH(min), C S ≥ VIH(min), tCK = min Precharge Standby Current in non power down mode ID D 2 N S C K E ≥ VIH(min), tCK = ∞ Input signals are stable. C K E ≤ VIL(max), tCK = min C K E ≤ VIL(max), tCK = ∞ C K E ≥ VIH(min), C S ≥ VIH(min), tCK = min Active Standby Current in non power down mode ID D 3 N S ID D 3 N Input signals are changed one time during 2CLKs. All other pins ≥ V D D 0.2V or ≤ 0.2V C K E ≥ VIH(min), tCK = ∞ Input signals are stable t C K ≥ tCK(min), Burst Mode Operating Current IDD4 tRAS ≥ tRAS(min), IO=0mA All banks active CL=2 110 110 CL=3 130 130 120 50 mA 15 ID D 2 N Input signals are changed one time during 2Clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 20 mA 1 mA ID D 2 P S 1 130 130 120 110 110 110 mA 2 -55 -6 -7 -8 -10 Unit Note Precharge Standby Current in power down mode ID D 3 P Active Standby Current in power down mode ID D 3 P S 30 mA 30 30 110 110 90 mA 3 Auto Refresh Current Self Refresh Current ID D 5 ID D 6 t R R C ≥ tRRC(min), All banks active C K E ≤ 0.2V 130 130 110 2 110 110 110 mA mA Note : 1.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s . 2.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V 3.ID D 1 a n d I DD4 depend on output loading and cycle rates. Specified values are measured with the output open. Rev. 3.6/Apr.01 6 HY57V161610D A C C H A R A C T E R IS T IC S ( T A = 0 °C t o 7 0 ° C , V D D = 3 . 0 V t o 3 . 6 V , V S S = 0 V Note1,2 ) -5 Parameter Symbol Min CL=3 CL=2 tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH 1.5 1.5 1 1.5 1 1.5 1 1.5 1 2 1.5 1 1.5 1 1.5 1 1.5 1 5 1.75 1.75 4.5 Max M i n 5.5 2 2 -55 Max M i n 6 10 2 2 5 2 1.5 1 1.5 1 1.5 1 1.5 1 -6 Max 5.5 6 M in 7 10 2.5 2.5 2.5 1.75 1 1.75 1 1.75 1 1.75 1 -7 Max 6 6 M in 8 12 3 3 2.5 2 1 2 1 2

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HY67V161610D

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