(HY5DU56xx22CT) 256M-P DDR SDRAM

www.DataSheet4U.com HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 256M-P DDR SDRAM HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 DESCRIPTION PRELIMINARY The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. FEATURES • • • • • • • VDD/VDDQ = 2.5 ~ 2.7V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe • • • • • • • • • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock CAS latency 3 supported Programmable burst length 2 / 4 / 8 with both sequential and interleave mode Internal four bank operations with single pulsed /RAS tRAS Lock-out function supported Auto refresh and Self refresh supported 8192 refresh cycles / 64ms JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Full and Half strength driver option controlled by EMRS • • ORDERING INFORMATION Part No. HY5DU56422CT-D* HY5DU56822CT-D* HY5DU561622CT-D* OPERATING FREQUENCY Package 400mil 66pin TSOP-II Configuration 64Mx4 32Mx8 16Mx16 Grade - D4 - D43 Speed 200MHz 200MHz Remark (CL-tRCD-tRP) DDR400 (3-4-4) DDR400 (3-3-3) * Note : D of speed indicates DDR400. Rev. 0.3 / Oct. 2003 3 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 PIN CONFIGURATION x4 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD DNU NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD DNU NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD DNU LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x8 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x4 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 400mil X 875mil 66pin TSOP -II 0.65mm pin pitch ROW AND COLUMN ADDRESS TABLE ITEMS Organization Row Address Column Address Bank Address Auto Precharge Flag Refresh 64Mx4 16M x 4 x 4banks A0 - A12 A0-A9, A11 BA0, BA1 A10 8K 32Mx8 8M x 8 x 4banks A0 - A12 A0-A9 BA0, BA1 A10 8K 16Mx16 4M x 16 x 4banks A0 - A12 A0-A8 BA0, BA1 A10 8K Rev. 0.3 / Oct. 2003 3 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 PIN DESCRIPTION PIN CK, /CK TYPE Input DESCRIPTION Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied. Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15. Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. CKE Input /CS Input BA0, BA1 Input A0 ~ A12 Input /RAS, /CAS, /WE Input DM (LDM, UDM) Input DQS (LDQS, UDQS) DQ VDD/VSS VDDQ/VSSQ VREF NC I/O I/O Supply Supply Supply NC Rev. 0.3 / Oct. 2003 4 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 FUNCTIONAL BLOCK DIAGRAM (64Mx4) 4Banks x 16Mbit x 4 I/O Double Data Rate Synchronous DRAM Write Data Register 2-bit Prefetch Unit 8 Bank Control 16Mx4 / Bank0 Sense AMP 16Mx4 / Bank1 Command Decoder 16Mx4 / Bank2 16Mx4 / Bank3 Mode Register Row Decoder 8 4 Input Buffer DQS DM 2-bit Prefetch Unit CLK /CLK CKE /CS /RAS /CAS /WE Output Buffer 4 DQ[0:3] Column Decoder ADD BA Address Buffer Column Address Counter CLK_DLL DQS Data Strobe Transmitter Data Strobe Receiver DQS CLK, /CLK DLL Block Mode Register Rev. 0.3 / Oct. 2003 5 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 FUNCTIONAL BLOCK DIAGRAM (32Mx8) 4Banks x 8Mbit x 8 I/O Double Data Rate Synchronous DRAM Write Data Register 2-bit Prefetch Unit 16 Bank Control 8Mx8 / Bank0 Sense AMP 8Mx8 / Bank1 Command Decoder 8Mx8 / Bank2 8Mx8 / Bank3 Mode Register Row Decoder 16 8 Input Buffer DQS DM 2-bit Prefetch Unit CLK /CLK CKE /CS /RAS /CAS /WE Output Buffer 8 DQ[0:7] Column Decoder ADD BA Address Buffer Column Address Counter CLK_DLL DQS Data Strobe Transmitter Data Strobe Receiver DQS CLK, /CLK DLL Block Mode Register Rev. 0.3 / Oct. 2003 6 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 FUNCTIONAL BLOCK DIAGRAM (16Mx16) 4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM Write Data Register 2-bit Prefetch Unit 32 Bank Control 4Mx16 / Bank0 Sense AMP 4Mx16 / Bank1 Command Decoder 4Mx16 / Bank2 4Mx16 / Bank3 Mode Register Row Decoder 32 16 Input Buffer LDQS, UDQS LDM, UDM 2-bit Prefetch Unit CLK /CLK CKE /CS /RAS /CAS /WE Output Buffer 16 DQ[0:15] Column Decoder ADD BA Address Buffer Column Address Counter CLK_DLL LDQS UDQS LDQS, UDQS Data Strobe Transmitter Data Strobe Receiver CLK, /CLK DLL Block Mode Register Rev. 0.3 / Oct. 2003 7 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 SIMPLIFIED COMMAND TRUTH TABLE Command Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit CKEn-1 H H H H H CKEn X X X X X CS L L H L L L RAS L L X H L H CAS L L X H H L WE L L X H H H CA RA L H L H H L X X ADDR A10/ AP OP code OP code X V V BA Note 1,2 1,2 1 1 1 1,3 1 1,4 1,5 1 1 1 1 X 1 1 X 1 1 1 1 X 1 1 H X L H L L CA V X V H H H H L X X H L H L L L L H L H L H L H L L H L L X H X H X H X V X H H L L X H X H X H X V L L H H X H X H X H X V X Entry Precharge Power Down Mode Exit H L L H Active Power Down Mode Entry Exit H L L H ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. LDM/UDM states are Don’t Care. Refer to be