(HY5DU56xx22A(L)T) 256M-S DDR SDRAM

www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T 256M-S DDR SDRAM HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T DataSheet4U.com DataShee This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/ May. 02 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Revision History 1. Revision 0.2 (Jan. 02) 1) Define Preliminary Specification 2. Revision 0.3 (Mar. 02) 1) Define IDD Specification 2) Added programmable Cas Latrency 1.5 3) Changed VREF value from min (0.49*VDDQ) & max (0.51*VDDQ) to min (VDDQ/2-50mV) & max (VDDQ/2+50mV) 4) Changed ILI (Input Leakage Current) value from +/- 5uA to +/- 2uA 3. Revision 0.4 (May. 02) 1) Added comment of Cas Latrency 1.5 & 3 et4U.com DataSheet4U.com DataShee Rev. 0.4/ May. 02 2 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T DESCRIPTION PRELIMINARY The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. FEATURES • • • • • • • VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) • • • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 1.5, 2, 2.5 and 3 supported Programmable burst length 2 / 4 / 8 with both sequential and interleave mode et4U.com • Internal four bank operations with single pulsed /RAS x16 device has two bytewide data strobes (UDQS, DataSheet4U.com LDQS) per each x8 I/O • tRAS Lock-out function supported Data outputs on DQS edges when read (edged DQ) • Auto refresh and Self refresh supported Data inputs on DQS centers when write (centered DQ) • 8192 refresh cycles / 64ms On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe • • JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Full and Half strength driver option controlled by EMRS DataShee • • ORDERING INFORMATION Part No. HY5DU56422A(L)T-X* HY5DU56822A(L)T-X* HY5DU561622A(L)T-X* OPERATING FREQUENCY Package 400mil 66pin TSOP-II Configuration 64Mx4 32Mx8 16Mx16 Grade -J -M -K -H -L CL2 133MHz 133MHz 133MHz 100MHz 100MHz CL2.5 166MHz 133MHz 133MHz 133MHz 125MHz Remark (CL-tRCD-tRP) DDR333 (2.5-3-3) DDR266 (2-2-2) DDR266A (2-3-3) DDR266B (2.5-3-3) DDR200 (2-2-2) * X means speed grade * CL1.5 @ DDR200 supported * CL3 supported Rev. 0.4 / May. 02 3 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T PIN CONFIGURATION x4 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD DNU NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD DNU NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD DNU LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 400mil X 875mil 15 16 66pin TSOP -II 17 18 0.65mm pin pitch 19 20 21 22 23 24 25 26 27 28 DataSheet4U.com 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x8 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x4 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS et4U.com DataShee ROW AND COLUMN ADDRESS TABLE ITEMS Organization Row Address Column Address Bank Address Auto Precharge Flag Refresh 64Mx4 16M x 4 x 4banks A0 - A12 A0-A9, A11 BA0, BA1 A10 8K 32Mx8 8M x 8 x 4banks A0 - A12 A0-A9 BA0, BA1 A10 8K 16Mx16 4M x 16 x 4banks A0 - A12 A0-A8 BA0, BA1 A10 8K Rev. 0.4/ May. 02 4 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T PIN DESCRIPTION PIN CK, /CK TYPE Input DESCRIPTION Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied. Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The DataSheet4U.com address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15. Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. CKE Input /CS Input BA0, BA1 Input A0 ~ A12 Input et4U.com DataShee /RAS, /CAS, /WE Input DM (LDM, UDM) Input DQS (LDQS, UDQS) DQ VDD/VSS VDDQ/VSSQ VREF NC I/O I/O Supply Supply Supply NC Rev. 0.4/ May. 02 5 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T FUNCTIONAL BLOCK DIAGRAM (64Mx4) 4Banks x 16Mbit x 4 I/O Double Data Rate Synchronous DRAM Write Data Register 2-bit Prefetch Unit 8 Bank Control Command Decoder 16Mx4 / Bank0 Sense AMP 16Mx4 / Bank1 16Mx4 / Bank2 16Mx4 / Bank3 Mode Register Row Decoder 8 4 Input Buffer DQS DM 2-bit Prefetch Unit CLK /CLK CKE /CS /RAS /CAS /WE Output Buffer 4 DQ[0:3] Column Decoder et4U.com DataSheet4U.com ADD BA Address Buffer Column Address Counter CLK_DLL DQS Data Strobe Transmitter Data Strobe Receiver DQS DataShee CLK, /CLK DLL Block Mode Register Rev. 0.4/ May. 02 6 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T FUNCTIONAL BLOCK DIAGRAM (32Mx8) 4Banks x 8Mbit x 8 I/O Double Data Rate Synchronous DRAM Write Data Register 2-bit Prefetch Unit 16 Bank Control Command Decoder 8Mx8 / Bank0 Sense AMP 8Mx8 / Bank1 8Mx8 / Bank2 8Mx8 / Bank3 Mode Register Row Decoder 16 8 Input Buffer DQS DM 2-bit Prefetch Unit CLK /CLK CKE /CS /RAS /CAS /WE Output Buffer 8 DQ[0:7] Column Decoder et4U.com ADD BA Address Buffer DataSheet4U.com Column Address Counter CLK_DLL DQS Data Strobe Transmitter Data Strobe Receiver DQS DataShee CLK, /CLK DLL Block Mode Register Rev. 0.4/ May. 02 7 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T FUNCTIONAL BLOCK DIAGRAM (16Mx16) 4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM Write Data Register 2-bit Prefetch Unit 32 Bank Control Command Decoder 4Mx16 / Bank0 Sense AMP 4Mx16 / Bank1 4Mx16 / Bank2 4Mx16 / Bank3 Mode Register Row Decoder 32 16 Input Buffer LDQS, UDQS LDM, UDM 2-bit Prefetch Unit CLK /CLK CKE /CS /RAS /CAS /WE Output Buffer 16 DQ[0:15] Column Decoder et4U.com DataSheet4U.com ADD BA Address Buffer Column Address Counter CLK_DLL LDQS UDQS LDQS, UDQS Da