(HY57V28820HC(L)T-L) 4Banks x 4M x 8bits Synchronous DRAM

www.DataSheet4U.com HY57V28820HC(L)T-I 4Banks x 4M x 8bits Synchronous DRAM DESCRIPTION The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range. f HY57V28820HC(L)T is organized as 4banks of 4,194,304x8. HY57V28820HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • • • Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation • • • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst • DataSheet4U.com • - 1, 2, 4 or 8 for Interleave Burst DataShee • • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. HY57V28820HCT-6I HY57V28820HCT-KI HY57V28820HCT-HI HY57V28820HCT-8I HY57V28820HCT-PI HY57V28820HCT-SI HY57V28820HCLT-6I HY57V28820HCLT-KI HY57V28820HCLT-HI HY57V28820HCLT-8I HY57V28820HCLT-PI HY57V28820HCLT-SI Clock Frequency 166MHz 133MHz 133MHz 125MHz 100MHz 100MHz 166MHz 133MHz 133MHz 125MHz 100MHz 100MHz Power Organization Interface Package Normal 4Banks x 4Mbits x8 LVTTL 400mil 54pin TSOP II Low power This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Jan. 02 1 DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com HY57V28820HC(L)T-I PIN CONFIGURATION VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS 54pin TSOP II 400mil x 875mil 0.8mm pin pitch et4U.com DataSheet4U.com DataShee PIN DESCRIPTION PIN CLK CKE CS BA0, BA1 A0 ~ A11 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection 2 RAS, CAS, WE DQM DQ0 ~ DQ7 VDD/VSS VDDQ/VSSQ NC Rev. 0.1/Jan. 01 DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com HY57V28820HC(L)T-I FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 8 I/O Synchronous DRAM Self refresh logic & timer Internal Row counter CLK CKE CS State Machine RAS CAS WE DQM Row active 4Mx8 Bank3 Row Pre Decoders 4Mx8 Bank 2 X decoders 4Mx8 Bank 1 X decoders 4Mx8 Bank 0 X decoders DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate X decoders refresh Column Active Memory Cell Array et4U.com Column Pre Decoders DataSheet4U.com Y decoders DQ6 DQ7 DataShee Bank Select Column Add Counter A0 A1 Address buffers A11 BA0 BA1 Address Registers Burst Counter Mode Registers CAS Latency Data Out Control Pipe Line Control Rev. 0.1/Jan. 01 3 DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com HY57V28820HC(L)T-I ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature ⋅ Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Symbol -40 ~ 85 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 ⋅ 10 Rating °C °C V V mA W °C ⋅ Sec Unit Note : Operation at above absolute maximum rating can adversely affect device reliability. DC OPERATING CONDITION (TA= -40 to 85°C) Parameter Power Supply Voltage Input High voltage Input Low voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 3.0 0 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1,2 1,3 et4U.com: Note DataSheet4U.com DataShee 1.All voltages are referenced to VSS = 0V 2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration. AC OPERATING TEST CONDITION Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage (TA= -40 to 85°C, VDD=3.3±0.3V, VSS=0V) Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 50 Unit V V ns V pF 1 Note Output Load Capacitance for Access Time Measurement Note : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit Rev. 0.1/Jan. 01 4 DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com HY57V28820HC(L)T-I CAPACITANCE (TA=25°C, f=1MHz) -6I/KI/HI Parameter Pin Symbol Min. Input Capacitance CLK A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM Data Input / Output Capacitance DQ0 ~ DQ7 CI1 CI2 CI/O 2.5 2.5 4 Max. 3.5 3.8 6.5 Min. 2.5 2.5 4 Max. 4 5 6.5 pF pF pF -8I/PI/SI Unit OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output 50pF Output 50pF et4U.com DataSheet4U.com DataShee DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (TA= -40 to 85°C, VDD=3.3±0.3V) Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ILI ILO VOH VOL Symbol Min. -1 -1 2.4 Max 1 1 0.4 Unit uA uA V V Note 1 2 IOH = -2mA IOL =+2mA Note : 1.VIN = 0 to 3.6V, All other pins are not under test = 0V 2.DOUT is disabled, VOUT=0 to 3.6V Rev. 0.1/Jan. 01 5 DataSheet4U.com DataSheet4 U .com www.DataSheet4U.com HY57V28820HC(L)T-I DC CHARACTERISTICS II (TA= -40 to 85°C, VDD=3.3±0.3V, VSS=0V) Speed Parameter Symbol Test Condition -6I Operating Current Precharge Standby Current in Power Down Mode IDD1 IDD2P IDD2PS IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS IDD3N Active Standby Current in Non Power Down Mode IDD3NS Burst Mode Operating Current .com Auto Refresh Current Self Refresh Current Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA CKE ≤ VIL(max), tCK = 15ns CKE ≤ VIL(max), tCK = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V CKE ≥ VIH(min), tCK = ∞ Input signals are stable. CKE ≤ VIL(max), tCK = 15ns CKE ≤ VIL(max), tCK = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V CKE ≥ VIH(min), tCK = ∞ Input signals are stable. tCK ≥ tCK(min), IOL=0mA All banks active CL=3 140 120 130 220 120 Unit -KI 110 Note -HI 110 2 -8I 110 -PI 100 -SI 100 mA 1 mA 1 15 mA 15 5 mA 5 30 mA 20 120 130 220 2 800 120 130 200 110 110 200 110 mA 110 200 mA mA uA 2 3 4 1 IDD4 IDD5 IDD6 et4U DataSheet4U.com 150 CL=2 240 DataShee tRRC ≥ tRRC(min), All banks active CKE ≤ 0.2V Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2.Min. of tRRC (Refresh RAS cycle time) is applied to HY57V28820HC(L)T-6I/KI/HI/8I/PI/SI which are listed on AC characteristic II. 3.HY57V28820HCT-6I/KI/HI/8I/PI/SI 4.HY57V28820HCLT-6I/KI/HI/8I/PI/SI 5. Rev. 0.1/Jan. 01 6 DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com HY57V28820HC(L)T-I AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -6I Parameter Symbol Min System Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 6 1000 10 2.5 2.5 2 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 2.7 5.4 6 5.4 5.4 7.5 2.5 2.5 2 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 2.7 5.4 5.4 Max Min 7.5 1000 10 2.5 2.5 2 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 5.4 6 Max Min 7.5 1000 10 3 3 2 2 1 2 1 2 1 2 1 6 6 6 6 Max Min 8 1000 10 3 3 2 2 1 2 1 2 1 2 1 1 3 3 6 6 6 6 Max Min 10 1000 12 3 3 2 2 1 2 1 2 1 2 1 1 3 3 6 6 6 6 Max Min 10 1000 ns ns ns ns 2 CAS Latency = 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 Max ns -KI -HI -8I -PI -SI Unit Note Clock High Pulse Width Clock Low Pulse Width Access Time From Clock CAS Latency = 3 Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to et4U.com Data Output in Low-Z Time