Description
www.DataSheet4U.com HY57V161610E 2 Banks x 512K x 16 Bit Synchronous DRAM DESCRIPTION THE Hynix HY57V161610E is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610E is organized as 2banks of 524,288x16. HY57V161610E is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.) FEATURES • • • • • • Single 3.0V to 3.6V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM/LDQM Internal two banks operation • • • • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequence Burst - 1, 2, 4 and 8 for Interleave Burst Programmable CAS Latency ; 1, 2, 3 Clocks ORDERING INFORMATION Part No. HY57V161610ET-5 HY57V161610ET-55 HY57V161610ET-6 HY57V161610ET-7 HY57V161610ET-8 HY57V161610ET-10 HY57V161610ET-15 Note : 1. VDD(min) of HY57V161610ET-5/55 is 3.15V Clock Frequency 200MHz 183MHz 166MHz 143MHz 125MHz 100MHz 66MHz Organization Interface Package 2Banks x 512Kbits x 16 LVTTL 400mil 50pin TSOP II This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied Rev. 0.2 / Aug. 2003 1 www.DataSheet4U.com HY57V161610E PIN CONFIGURATION V DD DQ0 DQ1 V SSQ DQ2 DQ3 V DDQ DQ4 DQ5 V SSQ DQ6 DQ7 VDDQ LDQM /WE /CAS /RAS /CS A11 A10 A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 V SS DQ15 DQ14 VSSQ DQ13 DQ12 50pin TSOP II 400mil x 825mil 0.8mm pin pitch VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTION PIN CLK CKE CS BA A0 ~ A10 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are referenced to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. Command input enable or mask except CLK, CKE and DQM Select either one of banks during both RAS and CAS activity. Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation. Refer function truth table for details DQM control output buffer in read mode and mask input data in write mode Multiplexed data input / output pin Power supply for internal circuit and input buffer Power supply for DQ No connection RAS, CAS, WE LDQM, UDQM DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ NC Rev. 0.2 / Aug. 2003 2 www.DataSheet4U.com HY57V161610E FUNCTIONAL BLOCK DIAGRAM 1Mx16 Synchronous DRAM Self Refresh Counter Row Addr. Latch/Predecoder Auto/Self Refresh Refresh Interval Timer Refresh Counter Row Decoder Address[0:10] Ref. Addr.[0:11] 512Kx16 Bank 0 Sense AMP & I/O gates Column Decoder DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CLK Row Active BA(A11) CS RAS CAS WE UDQM LDQM Column Active Overflow Column Addr. Latch & Counter Burst Length Counter Column Decoder Sense AMP & I/O gates Row Addr. Latch/Predecoder 512Kx16 Bank 1 Mode Register Test Mode I/O Control Rev. 0.2 / Aug. 2003 Data Input/Output Buffers CKE Precharge Address Register State Machine 3 www.DataSheet4U.com HY57V161610E ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature·Time TA TSTG VIN, VOUT VDD IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260·10 Rating °C °C V V mA W °C ·Sec Unit Note : Operation at above absolute maximum rating can adversely affect device reliability. DC OPERATING CONDITION (TA=0°C to 70°C) Parameter Power Supply Voltage Input high voltage Input low voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Typ. 3.3 3.0 0 Max 3.6 VDD + 0.3 0.8 Unit V V V Note 1, 2, 3 1, 4 1, 5 Note : 1.All voltages are referenced to VSS = 0V. 2.VDD(min) is 3.15V when HY57V161610ET-7 operates at CAS latency=2 3.VDD(min) of HY57V161610ET-5/55 is 3.15V 4.Vih(Max) : 4.6V AC pulse width with < 3ns of duration. 5.Vil(min) : -1.5V AC pulse width with < 3ns of duration. AC OPERATING CONDITION (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0V) Parameter AC input high / low level voltage Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 30 Unit V V ns V pF 1 Note Note : 1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF). For details, refer to AC/DC output load circuit. 2. VDD(min) is 3.15V when HY57V161610ET-7 operates at CAS latency=2 and tCK2=8.9ns 3. VDD(min) of HY57V161610ET-5/55 is 3.15V‘ Rev. 0.2 / Aug. 2003 4 HY57V161610E CAPACITANCE (TA=25°C, f=1MHz) Parameter CLK Input capacitance A0 ~ A10, BA CKE, CS, RAS, CAS, WE, UDQM, LDQM DQ0 ~ DQ15 Pin Symbol CI1 CI2 CI/O Min 2.5 2.5 4 Max 4 5 6.5 Unit pF pF pF Data input / output capacitance OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Ω Output 30pF Output 30pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (TA=0°C to 70°C) Parameter Power Supply Voltage Input leakage current Output leakage current Output high voltage Output low voltage VDD IL IO VOH VOL Symbol Min. 3.0 -1 -1 2.4 Max 3.6 1 1 0.4 Unit V uA uA V V Note 1, 2 3 4 IOH = -4mA IOL =+4mA Note : 1.VDD(min) is 3.15V when HY57V161610ET-7 operates at CAS latency=2 and tCK2=8.9ns. 2.VDD(min) of HY57V161610ET-5/55 is 3.15V 3.VIN = 0 to 3.6V, All other pins are not under test = 0V 4.DOUT is disabled, VOUT=0 to 3.6V Rev. 0.2 / Aug. 2003 5 w w w . D a t a S h e e t 4 U . c o m HY57V161610E DC CHARACTERISTICS II (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0VNote1,2) Speed Parameter Symbol Test Condition -5 Operating Current IDD1 Burst Length=1, One bank active tRAS ≥ tRAS(min),tRP ≥ tRP(min), IO=0mA CKE ≤ VIL(max), tCK = 15ns CKE ≤ VIL(max), tCK = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2Clks. All other pins ≥ VDD-0.2V or ≤ 0.2V CKE ≥ VIH(min), tCK = ∞ Input signals are stable. CKE ≤ VIL(max), tCK = min CKE ≤ VIL(max), tCK = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min Input signals are changed one time during 2CLKs. All other pins ≥ VDD0.2V or ≤ 0.2V CKE ≥ VIH(min), tCK = ∞ Input signals are stable tCK ≥ tCK(min), tRAS ≥ tRAS(min), IO=0mA All banks active CL=3 CL=2 CL=1 130 130 130 130 120 110 110 2 130 -55 130 -6 120 -7 110 2 mA 1 -8 110 -10 110 -15 100 mA 2 Unit Note Precharge Standby Current in power down mode IDD2P IDD2PS Precharge Standby Current in non power down mode IDD2N 25 mA 15 3.0 mA 3.0 IDD2NS IDD3P IDD3PS Active Standby Current in power down mode Active Standby Current in non power down mode IDD3N 50 mA 30 110 110 110 110 110 90 110 80 70 100 mA mA mA 3 IDD3NS Burst Mode Operating Current IDD4 Auto Refresh Current Self Refresh Current IDD5 IDD6 tRRC ≥ tRRC(min), All banks active CKE ≤ 0.2V Note : 1.VDD(min) is 3.15V when HY57V161610ET-7 operates at CAS latency=2 and tCK2=8.9ns. 2.VDD(min) of HY57V161610ET-5/55 is 3.15V 3.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. Rev. 0.2 / Aug. 2003 6 w w w . D a t a S h e e t 4 U . c o m HY57V161610E AC CHARACTERISTICS Parameter Symbol Min CL=3 System clock cycle time CL=2 CL=1 Clock high pulse width Clock low pulse width CL=3 Access time from clock CL=2 CL=1 Data-out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time CLK to data output in low Ztime CLK to data output in high Z-time tCK3 tCK2 tCK1 tCHW tCLW tAC3 tAC2 tAC1 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ 1.5 1.5 1 1.5 1 1.5 1 1.5 1 2 2 5 2 1.5 1 1.5 1 1.5 1 1.5 1 2 2 5.5 5 2 2 4.5 Max Min 5.5 2 2 5 Max Min 6 10 2 2 2 1.5 1 1.5 1 1.5 1 1.5 1 2 2 Max 5.5 6 6 Min 7 10 2.5 2.5 2.5 1.75 1 1.75 1 1.75 1 1.75 1 2 2 Max 6 6 7 ns ns ns ns ns ns ns ns ns ns ns 4 4 4 4 4 4 4 4 ns 3 ns ns 4 4 ns 3 (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0VNote1,2) -5 -55 -6 -7 Unit Note Rev. 0.2 / Aug. 2003 7 www.DataSheet4U.com HY57V161610E AC CHARACTERISTICS Parameter (TA=0°C to 70°C, VDD=3.0V to 3.6V, VSS=0VNote1,2) -8 Symbol Min Max 6 6 8 Min 10 12 3 3 2.5 2.5 1 2.5 1 2.5 1 2.5 1 2 3 Max 7 7 10 Min 15 15 15 3 3 2.5 2.5 1 2.5 1 2.5 1 2.5 1 2 3 Max 7 7 14 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -10 -15 - continued - Unit Note CL=3 System clock cycle time CL=2 CL=1 Clock high pulse width Clock low pul

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