2K x 8 CMOS PROM

HM-6617/883 March 1997 2K x 8 CMOS PROM Description The HM-6617/883 is a 16,384-bit fuse link CMOS PROM in a 2K word by 8-bit/word format with “Three-State” outputs. This PROM is available in the standard 0.600 inch wide 24 pin SBDIP, the 0.300 inch wide slim SBDIP, and the JEDEC standard 32 pad CLCC. The HM-6617/883 utilizes a synchronous design technique. This includes on-chip address latches and a separate output enable control which makes this device ideal for applications utilizing recent generation microprocessors. This design technique, combined with the Intersil advanced self-aligned silicon gate CMOS process technology offers ultra-low standby current. Low ICCSB is ideal for battery applications or other systems with low power requirements. The Intersil NiCr fuse link technology is utilized on this and other Intersil CMOS PROMs. This gives the user a PROM with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. NiCr fuse technology combined with the low power characteristics of CMOS provides an excellent alternative to standard bipolar PROMs or NMOS EPROMs. All bits are manufactured storing a logical “0” and can be selectively programmed for a logical “1” at any bit location. Features • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Low Power Standby and Operating Power - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz • Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns • Industry Standard Pinout • Single 5.0V Supply • CMOS/TTL Compatible Inputs • High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads • Synchronous Operation • On-Chip Address Latches • Separate Output Enable • Operating Temperature Range . . . . . . -55oC to +125oC Ordering Information PACKAGE SBDIP SLIM SBDIP CLCC TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC -55oC to +125oC 90ns HM1-6617B/883 HM6-6617B/883 HM4-6617B/883 120ns HM1-6617B/883 HM6-6617B/883 HM4-6617B/883 PACKAGE NO. D24.6 D24.3 J32.A Pinouts HM-6617/883 (SBDIP) TOP VIEW A7 HM-6617/883 (CLCC) TOP VIEW VCC NC NC NC NC NC PIN DESCRIPTION PIN 29 A8 28 A9 27 NC 26 P 25 G 24 A10 23 E 22 Q7 21 Q6 DESCRIPTION No Connect Address Inputs Chip Enable Data Output Power (+5V) Output Enable Program Enable A7 A6 A5 A4 A3 A2 A1 A0 Q0 1 2 3 4 5 6 7 8 9 24 VCC 23 A8 22 A9 21 P 20 G 19 A10 18 E 17 Q7 16 Q6 15 Q5 14 Q4 13 Q3 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 Q0 13 3 2 1 32 31 30 NC A0-A10 E Q VCC G P (Note) Q1 10 Q2 11 GND 12 14 15 16 17 18 19 20 Q1 Q2 Q3 Q4 GND NC Q5 NOTE: P should be hardwired to VCC except during programming. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 3016.1 6-250 HM-6617/883 Functional Diagram MSB A10 A9 A8 A7 A6 A5 A4 A LATCHED ADDRESS REGISTER A 7 LSB L G 16 16 16 16 16 16 16 16 G E GATED COLUMN DECODER AND DATA OUTPUT CONTROL A 4 G L ALL LINES POSITIVE LOGIC: ACTIVE HIGH MSB A3 A2 A1 A0 THREE-STATE BUFFERS: A HIGH OUTPUT ACTIVE ADDRESS LATCHES AND GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G LATCHED ADDRESS REGISTER LSB A 4 Q6 Q7 8 Q3 Q4 Q5 Q2 7 GATED ROW DECODER 128 x 128 MATRIX Q0 Q1 128 6-251 HM-6617/883 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance θJA θJC SBDIP Package . . . . . . . . . . . . . . . . . . 48oC/W 9oC/W Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 65oC/W 14oC/W CLCC Package . . . . . . . . . . . . . . . . . . 58oC/W 19oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . +2.4V to VCC +0.3V Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5473 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. HM-6617/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current SYMBOL VOH1 VOL IIOZ (NOTES 1, 4) CONDITIONS VCC = 4.5V, IO = -2.0mA VCC = 4.5V, IO = +4.8mA VCC = 5.5V, G = 5.5V, VI/O = GND or VCC VCC = 5.5V, VI = GND or VCC, P Not Tested VI = VCC or GND, VCC = 5.5V, IO = 0mA VCC = 5.5V, G = GND, (Note 3), f = 1MHz, IO = 0mA, VI = VCC or GND VCC = 4.5V (Note 6) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC MIN 2.4 -1.0 MAX 0.4 1.0 UNITS V V µA µA µA II 1, 2, 3 -1.0 1.0 Standby Supply Current ICCSB 1, 2, 3 - 100 Operating Supply Current ICCOP 1, 2, 3 - 20 mA Functional Test FT 7, 8A, 8B -55oC ≤ TA ≤ +125oC - - TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS LIMITS HM-6617B/883 HM-6617/883 PARAMETER Address Access Time SYMBOL TAVQV (NOTES 1, 2, 4) CONDITIONS VCC = 4.5V and 5.5V (Note 5) VCC = 4.5V and 5.5V GROUP A SUBGROUPS 9, 10, 11 TEMPERATURE -55oC ≤ TA ≤ +125oC MIN - MAX 105 MIN - MAX 140 UNITS ns Output Enable Access Time Chip Enable Access Time Address Setup Time Address Hold Time Chip Enable Low Width Chip Enable High Width TGLQV 9, 10, 11 -55oC ≤ TA ≤ +125oC - 40 - 50 ns TELQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 90 - 120 ns TAVEL TELAX TELEH TEHEL VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC 15 20 95 40 - 20 25 120 40 - ns ns ns ns 6-252 HM-6617/883 TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested LIMITS LIMITS HM-6617B/883 HM-6617/883 PARAMETER Read Cycle Time SYMBOL TELEL (NOTES 1, 2, 4) CONDITIONS VCC = 4.5V and 5.5V GROUP A SUBGROUPS 9, 10, 11 TEMPERATURE -55oC ≤ TA ≤ +125oC MIN 136 MAX - MIN 160 MAX - UNITS ns NOTES: 1. All voltages referenced to Device GND. 2. AC measurements assume transition time ≤ 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equivalent load and CL ≅ 50pF. 3. Typical derating = 5mA/MHz increase in ICCOP. 4. All tests performed with P hardwired to VCC. 5. TAVQV = TELQV + TAVEL. 6. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH ≥ 1.5V, VOL ≤ 1.5V. TABLE 3. HM-6617/883 AC AND DC ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS HM-6617B/883 PARAMETER Input Capacitance LIMITS HM-6617/883 MIN - SYMBOL CIN (NOTES 1, 2) CONDITIONS VCC = Open, f = 1MHz, All Measurements Referenced to Device GND VCC = Open, f = 1MHz, All Measurements Referenced to Device GND NOTES 2, 3 TEMPERATURE +25oC MIN - MAX 10 MAX 10 UNITS pF 2, 4 2, 5 2, 3 +25oC +25oC +25oC - 12 10 12 - 12 10 12 pF pF pF I/O Capacitance CI/O VCC = Open, f = 1MHz, All Measurements Referenced to Device GND VCC = Open, f = 1MHz, All Measurements Referenced to Device GND 2, 4 2, 5 2 2 2 2 2 +25oC +25oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC -55oC ≤ TA ≤ +125oC 5 5 VCC1V 14 12 45 40 - 5 5 VCC1V 14 12 50 50 - pF pF ns ns ns ns V Chip Enable Time Output Enable Time Chip Disable Time Output Disable Time Output High Voltage TELQX TGLQX TEHQZ TGHQZ VOH2 VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V, IO = 100µA NOTES: 1. All tests performed with P hardwired to VCC. 2. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design changes which would affect these characteristics. 3. Applies to 0.600 inch SBDIP device types only. 4. Applies to 0.300 inch SBDIP device types only. 5. Applies to Ceramic Leadless Chip Carrier (CLCC) device types only. 6-253 HM-6617/883 TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 Switching Waveforms TAVQV VALID ADDRESS TAVEL TELAX TELEH E 1.5V TEHEL G 1.5V TGLQX TGHQZ DATA OUTPUT Q0-Q7 TELQX VALID DATA TS 1.5V TELQV TGLQV 1.5V 0V 1.5V TEHQZ 3.0V 1.5V 0V 3.0V VALID ADDRESSES TELEL 3.0V 0V ADDRESSES 1.5V 1.5V FIGURE 1. READ CYCLE Test Circuit DUT CL (NOTE) IOH NOTE: TEST HEAD CAPACITANCE ± 1.5V IOL EQUIVALENT CIRCUIT FIGURE 2. TEST CIRCUIT 6-254 HM-6617/883 Burn-In Circuits HM-6617