(Dot Matrix Liquid Crystal Display Controller/Driver)

HD66710 (Dot Matrix Liquid Crystal Display Controller/Driver) Description The HD66710 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, numbers, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimum system can be interfaced with this controller/driver. A single HD66710 is capable of displaying a single16-character line, two 16-character lines, or up to four 8-character lines. The HD66710 software is upwardly compatible with the LCD-II (HD44780) which allows the user to easily replace an LCD-II with an HD66710. In addition, the HD66710 is equipped with functions such as segment displays for icon marks, a 4-line display mode, and a horizontal smooth scroll, and thus supports various display forms. This achieves various display forms. The HD66710 character generator ROM is extended to generate 240 5 × 8 dot characters. The low voltage version (2.7V) of the HD66710, combined with a low power mode, is suitable for any portable battery-driven product requiring low power dissipation. Features • 5 × 8 dot matrix possible • Low power operation support:  2.7V to 5.5V (low voltage) • Booster for liquid crystal voltage  Two/three times (13V max.) • Wide range of liquid crystal display driver voltage  3.0V to 13V • Extension driver interface • High-speed MPU bus interface (2 MHz at 5-V operation) • 4-bit or 8-bit MPU interface capability • 80 × 8-bit display RAM (80 characters max.) 291 HD66710 • 9,600-bit character generator ROM  240 characters (5 × 8 dot) • 64 × 8-bit character generator RAM  8 characters (5 × 8 dot) • 8 × 8-bit segment RAM  40-segment icon mark • 33-common × 40-segment liquid crystal display driver • Programmable duty cycle (See List 1) • Wide range of instruction functions:  Functions compatible with LCD-II: Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift  Additional functions: Icon mark control, 4-line display, horizontal smooth scroll, 6-dot character width control, white-black inverting blinking cursor • Software upwardly compatible with HD44780 • Automatic reset circuit that initializes the controller/driver after power on • Internal oscillator with an external resistor • Low power consumption • QFP1420-100 pin, TQFP1414-100 pin bare-chip List 1 Programmable Duty Cycles Displayed Character 5 × 8-dot 5 × 8-dot 5 × 8-dot Maximum Number of Displayed Characters Single-Chip Operation One 16-character line + 40 segments Two 16-character lines + 40 segments Four 8-character lines + 40 segments Number of Lines 1 2 4 Duty Ratio 1/17 1/33 1/33 Ordering Information Type No. HD66710A00FS HD66710A00TF HCD66710A00 Package QFP1420-100 (FP-100A) TQFP1414-100 (TFP-100B) Chip CGROM Japanese standard 292 HD66710 LCD-II Family Comparison Item LCD-II (HD44780U) HD66702R 5V ±10% (standard) 2.7V to 5.5V (low voltage) 3.0V to 8.3V 20 characters × 2 lines HD66710 2.7V to 5.5V HD66712U 2.7V to 5.5V Power supply voltage 2.7V to 5.5V Liquid crystal drive voltage Maximum display digits per chip 3.0V to 11V 8 characters × 2 lines 3.0V to 13.0V 16 characters × 2 lines/ 8 characters × 4 lines 40 segments 2.7V to 11.0V 24 characters × 2 lines/ 12 characters × 4 lines 60 segments 1/17 and 1/33 9,600 bits (240 5 × 8 dot characters) Segment display Display duty cycle CGROM None None 1/8, 1/11, and 1/16 1/8, 1/11, and 1/16 1/17 and 1/33 9,920 bits (208 5 × 8 dot characters and 32 5 × 10 dot characters) 64 bytes 80 bytes None 40 16 A External (adjustable) Extenal resistor or external clock 270 kHz ±30% (59 to 110 Hz for 1/8 and 1/16 duty cycle; 43 to 80 Hz for 1/11 duty cycle) 91 kΩ: 5-V operation; 75 kΩ: 3-V operation None 7,200 bits (160 5 × 7 dot characters and 32 5 × 10 dot characters) 64 bytes 80 bytes None 100 16 B External (adjustable) 9,600 bits (240 5 × 8 dot characters) CGRAM DDRAM SEGRAM Segment signals Common signals Liquid crystal drive waveform Bleeder resistor for LCD power supply Clock source Rf oscillation frequency (frame frequency) 64 bytes 80 bytes 8 bytes 40 33 B External (adjustable) 64 bytes 80 bytes 16 bytes 60 34 B External (adjustable) External resistor or External resistor or External resistor or external clock external clock external clock 320 kHz ±30% (70 to 130 Hz for 1/8 and 1/16 duty cycle; 51 to 95 Hz for 1/11 duty cycle) 68 kΩ: 5-V operation; 56 kΩ: (3-V operation) None 270 kHz ±30% (56 to 103 Hz for 1/17 duty cycle; 57 to 106 Hz for 1/33 duty cycle) 91 kΩ: 5-V operation; 75 kΩ: 3-V operation) 2-3 times stepup circuit 270 kHz ±30% (56 to 103 Hz for 1/17 duty cycle; 57 to 106 Hz for 1/33 duty cycle) 130 kΩ: 5-V operation; 110 kΩ: 3-V operation 2-3 times stepup circuit Rf resistance Liquid crystal voltage booster circuit 293 HD66710 Item Extension driver control signal Reset function LCD-II (HD44780U) Independent control signal Power on automatic reset LCD-II (HD44780) 1 or 2 None Character unit 4 bits/8 bits 2 MHz: 5-V operation; 1 MHz: 3-V operation QFP-1420-80 80-pin bare chip HD66702R Independent control signal Power on automatic reset Fully compatible with the LCD-II 1 or 2 None Character unit 4 bits/8 bits 1 MHz HD66710 Used in common with a driver output pin Power on automatic reset Upper compatible with the LCD-II 1, 2, or 4 Available Dot unit 4 bits/8 bits 2 MHz: 5-V operation; 1 MHz: 3-V operation QFP-1420-100 100-pin bare chip TQFP1414-100 HD66712U Independent control signal Power on automatic reset or reset input Upper compatible with the LCD-II 1, 2, or 4 Available Dot unit Serial; 4 bits/8 bits 2 MHz: 5-V operation; 1 MHz: 3-V operation TCP-128 128-pin bare chip Instructions Number of displayed lines Low power mode Horizontal scroll Bus interface CPU bus timing Package LQFP-2020-144 144-pin bare chip 294 HD66710 HD66710 Block Diagram OSC1 OSC2 EXT CPG Reset circuit ACL Timing generator 7 Instruction register (I R) Instruction decoder COM1– COM33 33-bit shift register Common signal driver 8 Address counter 7 RS R/W E MPU interface Display data RAM (DDRAM) 80 × 8 bits 7 8 SEG1– SEG36 40-bit shift register 40-bit latch circuit DB4–DB7 Input/ output buffer 8 Data register (DR) 8 Busy flag 3 7 8 Segment signal driver SEG37/CL1 SEG38/CL2 SEG39/D SEG40/M DB3–DB0 8 8 Vci Segment RAM (SGRAM) 8 bytes Character generator RAM (CGRAM) 64 bytes Character generator ROM (CGROM) 9,600 bytes Cursor and bling controller LCD drive voltage selector C1 C2 V5OUT2 V5OUT3 Booster 5 5/6 Parallel/serial converter and attribute circuit VCC GND V1 V2 V3 V4 V5 295 HD66710 HD66710 Pin Arrangement SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37/CL1 SEG38/CL2 SEG39/D SEG40/M COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 VCC TEST EXT DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 E R/W RS OSC2 OSC1 Vci C2 C1 GND V5OUT2 V5OUT3 V5 V4 HD66710 (FP-100A) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 296 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM33 V1 V2 V3 (Top view) HD66710 HD66710 Pin Arrangement (TQFP1414-100 Pin) SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37/CL1 SEG38/CL2 SEG39/D SEG40/M COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG3 SEG2 SEG1 VCC TEST EXT DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 E R/W RS OSC2 OSC1 Vci C2 C1 GND V5OUT2 V5OUT3 HD66710 (TFP-100B) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 COM30 COM31 COM32 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM33 V1 V2 V3 V4 V5 (Top view) 297 HD66710 HD66710 Pad Arrangement Chip size (X × Y) : : Coordinate : Origin Pad size (X × Y) : 1 100 5.36 mm × 6.06 mm Pad center Chip center 100 µm × 100 µm 81 80 2 HD66710 Type code 79 Y 29 52 30 31 X 50 51 298 HD66710 HD66710 Pad Location Coordinates Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pad Name SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM33 V1 V2 V3 X –2495 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2695 –2495 –2051 –1701 –1498 –1302 –1102 –899 –700 –500 –301 –101 99 302 502 698 887 1077 1266 1488 1710 2063 Y 2910 2730 2499 2300 2100 1901 1698 1498 1295 1099 900 700 501 301 98 –113 –302 –501 –701 –900 –1100 –1303 –1502 –1702 –1901 –2101 –2300 –2500 –2731 –2