REJ09B0078-0300Z
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
16
H8S/2168Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2168 H8S/2167 H8S/2166 HD64F2168 HD64F2167 HD64F2166
Rev.3.00 Revision Date: Mar. 12, 2004
Rev. 3.00, 03/04, page ii of xl
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev. 3.00, 03/04, page iii of xl
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.
Rev. 3.00, 03/04, page iv of xl
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 3.00, 03/04, page v of xl
Preface
This LSI is a microcomputer (MCU) made up of the H8S/2000 CPU with Renesas Technology's original architecture as its core, and the peripheral functions required to configure a system, eg PC server. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU. This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a 16-bit free running timer (FRT), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication interface (SCI), an I2C bus interface (IIC), an LPC interface (LPC), a D/A converter, an A/D converter, and I/O ports as on-chip peripheral modules required for system configuration. A data transfer controller (DTC) is included as a bus master. A flash memory (F-ZTATTM*) version is available for this LSI’s 256, 384, and 512-kbyte ROM. The CPU and ROM are connected to a 16-bit bus, enabling byte data and word data to be accessed in a single state. This improves the instruction fetch and process speeds. Two operating modes are provided, offering a choice of address space and single chip mode/external extended mode. Boot programming into a flash memory, on-chip emulation, and boundary scan can be selected as special operating modes. Note: * F-ZTATTM is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who use this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Notes on reading this manual: • In order to understand the overall functions of the chip Read this manual in the order of the table of contents. This manual can be roughly categorized into the descriptions on the CPU, system control functions, peripheral functions and electrical characteristics.
Rev. 3.00, 03/04, page vi of xl
• In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. • In order to understand the detailed function of a register whose name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 24, List of Registers. Rules: Register name: The following notation is used for cases when the same or a similar function, e.g., serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel numb
