HD61203U
(Dot Matrix Liquid Crystal Graphic Display 64-Channel Common Driver)
ADE-207-274(Z) '99.9 Rev. 0.0 Description
The HD61203U is a common signal driver for dot matrix liquid crystal graphic display systems. It generates the timing signals (switch signal to convert LCD waveform to AC, frame synchronous signal) and supplies them to the column driver to control display. It provides 64 driver output lines and the impedance is low enough to drive a large screen. As the HD61203U is produced by a CMOS process, it is fit for use in portable battery-driven equipment utilizing the liquid crystal display’s low power consumption. The user can easily construct a dot matrix liquid crystal graphic display system by combining the HD61203U and the column (segment) driver HD61202U.
Features
• • • • • Dot matrix liquid crystal graphic display common driver with low impedance Low impedance: 1.5 kΩ max Internal liquid crystal display driver circuit: 64 circuits Internal dynamic display timing generator circuit Display duty cycle When used with the column driver HD61202U: 1/48, 1/64, 1/96, 1/128 When used with the controller HD61830: Selectable out of 1/32 to 1/128 Low power dissipation: During displays: 5 mW Power supplies: VCC: 2.7~5.5V Power supply voltage for liquid crystal display drive: 8V to 16V CMOS process 100-pin plastic QFP, 100-pin plastic TQFP, chip
• • • • •
1
HD61203U
Ordering Information
Type No. HD61203UFS HD61203UTE HCD61203U Package 100-pin plastic QFP (FP-100A) 100-pin thin plastic QFP (TFP-100B) Chip
2
HD61203U
Pin Arrangement
X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 X22 X21 X20 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 VEE V6L V5L V2L V1L VCC DL FS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
HD61203UFS (FP-100A)
DS1 DS2 C NC R NC CR STB SHL GND NC M/S ø2 ø1 NC FRM M NC FCS DR
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
X43 X44 X45 X46 X47 X48 X49 X50 X51 X52 X53 X54 X55 X56 X57 X58 X59 X60 X61 X62 X63 X64 VEE V6R V5R V2R V1R TH CL2 CL1
(Top view)
3
HD61203U
X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 X43 X44 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 VEE V6L V5L V2L V1L VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
HD61203UTFIA (TFP-100B)
4
DL FS DS1 DS2 C NC R NC CR STB SHL GND NC M/S ø2 ø1 NC FRM M NC FCS DR CL1 CL2 TH
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
X45 X46 X47 X48 X49 X50 X51 X52 X53 X54 X55 X56 X57 X58 X59 X60 X61 X62 X63 X64 VEE V6R V5R V2R V1R
(Top view)
HD61203U
Pad Arrangement
No.1 NO.79
NO.2
NO.78
Chip Size Coordinate Origin
: 3.40 × 4.08 µm2 : Pad Center : Chip center : 90 × 90 µm2
NO.28
TYPE CODE HD61203U
NO.54
Pad Size
No.29
No.52
Pad Location Coordinates
PAD PAD No. Name 1 X22 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 X21 X20 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 VEE1 V6L V5L V2L V1L VCC DL FS DS1 DS2 C X Coordinate Y 1853 1712 1544 1385 1238 1091 952 822 692 562 432 302 172 42 –88 –218 –349 –479 –609 –739 –869 –999 –1129 –1259 –1389 –1527 –1665 –1821 –1853 –1853 –1828 –1828 –1828 PAD No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 V1R V2R V5R V6R VEE2 X64 X63 X62 X61 X60 X59 X58 X57 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 –1522 –1374 –1236 –1097 –967 –837 –707 –577 –447 –317 –187 –57 73 CL2 1407 –1828 FCS DR 715 853 –1828 –1828 M/S PHI2 PHI1 FRM M 65 195 325 455 585 –1828 –1828 –1828 –1828 –1828 SHL GND –196 –65 –1828 –1828 CR –456 –1828 R –586 –1828 PAD Name Coordinate X Y PAD No. 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PAD Name X56 X55 X54 X53 X52 X51 X50 X49 X48 X47 X46 X45 X44 X43 X42 X41 X40 X39 X38 X37 X36 X35 X34 X33 X32 X31 X30 X29 X28 X27 X26 X25 X24 X23 X Coordinate Y 203 333 463 593 723 853 983 1122 1261 1399 1546 1693 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853
–1479 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1375 –1213 –976 –846 –716
1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1470 1304 1170 1040 910 779 649 519 389 259 129 –1 –131 –261 –391 –521 –651 –781 –911 –1041 –1171 –1301
5
6 V2R V6R X1 X2 64 output terminals X62 X63 X64 V1R V5R Liquid crystal display driver circuits 1 2 Bidirectional shift register 62 63 64 Logic DR Logic Timing generation circuit Logic C M/S FS DS1 DS2 ø1 ø2 FCS M CL2 FRM
V2L V6L
HD61203U
Block Diagram
V1L V5L
VCC GND VEE
CL1
TH
DL
Logic
SHL
STB
Oscillator
R CR
Rf Cf
HD61203U
Block Functions
Oscillator The CR oscillator generates display timing signals and operating clocks for the HD61202U. It is required when the HD61203U is used with the HD61202U. An oscillation resister Rf and an oscillation capacitor Cf are attached as shown in Figure 1. When using an external clock, input the clock into terminal CR and don’t connect any lines to terminals R and C. The oscillator is not required when the HD61203U is used with the HD61830. Then, connect terminal CR to the high level and don’t connect any lines to terminals R and C (Figure 2).
R
CR
C
R Open
CR
C
Rf
Cf
External Open clock
Figure 1 Oscillator Connection with HD61202U
R Open
CR VCC
C Open
Figure 2 Oscillator Connection with HD61830
7
HD61203U
Timing Generator Circuit The timing generator circuit generates display timing and operating clock for the HD61202U. This circuit is required when the HD61203U is used with the HD61202U. Connect terminal M/S to high level (master mode). It is not necessary when the display timing signal is supplied from other circuits, for example, from HD61830. In this case connect the terminals FS, DS1, and DS2 to high level and M/S to low level (slave mode). Bidirectional Shift Register A 64-bit bidirectional shift register. The data is shifted from DL to DR when SHL is at high level and from DR to DL when SHL is at low level. In this case, CL2 is used as shift clock. The lowest order bit of the bidirectional shift register, which is on the DL side, corresponds to X1 and the highest order bit on the DR side corresponds to X64. Liquid Crystal Display Driver Circuit The combination of the data from the shift register with the M signal allows one of the four liquid crystal display driver levels V1, V2, V5 and V6 to be transferred to the output terminals (Table 1). Table 1 Output Levels
M 1 1 0 0 Output Level V2 V6 V1 V5
Data from the Shift Register 1 0 1 0
8
HD61203U
HD61203U Terminal Functions
Terminal Name VCC GND VEE V1L, V2L V5L, V6L V1R, V2R V5R, V6R Number of Terminals 1 1 2 8 I/O Connected to Power supply Functions VCC–GND: Power supply for internal logic. VCC–VEE: Power supply for driver circuit logic. Power supply Liquid crystal display driver level power supply. V1L (V1R), V2L (V2R): Selected level V5L (V5R), V6L (V6R): Non-selected level Voltages of the level power supplies connected to V1L and V1R should be the same. (This applies to the combination of V2L & V2R, V5L & V5R and V6L & V6R respectively.) 1 I VCC or GND Selects master/slave. • M/S = VCC: Master mode When the HD61203U is used with the HD61202U, timing generation circuit operates to supply display timing signals and operation clock to the HD61202U. Each of I/O common terminals DL, DR, CL2, and M is in the output state. M/S = GND: Slave mode The timing operation circuit stops operating. The HD61203U is used in this mode when combined with the HD61830. Even if combined with the HD61202U, this mode is used when display timing signals (M, data, CL2, etc.) are supplied by another HD61203U in the master mode. Terminals M and CL2 are in the input state.
M/S
•
When SHL is VCC, DL is in the input state and DR is in the output state. When SHL is GND, DL is in the output state and DR is in the input state. FCS 1 I VCC or GND Selects shift clock phase. • FCS = VCC Shift register operates at the rising edge of CL2. Select this condition when HD61203U is used with HD61202U or when MA of the HD61830 connects to CL2 in combination with the HD61830. FCS = GND Shift register operates at the fall of CL2. Select this condition when CL1 of HD61830 connects to CL2 in combination with the HD61830.
•
9
HD61203U
Terminal Name FS Number of Terminals 1 I/O I Connected to Functions VCC or GND Selects frequency. When the frame frequency is 70 Hz, the oscillation frequency should be: f OSC = 430 kHz at FCS = VCC f OSC = 215 kHz at FCS = GND This terminal is active only in the master mode. Connect it to VCC in the slave mode. DS1, DS2 2 I VCC or GND Selects display duty factor. Display Duty Factor DS1 DS2 1/48 GND GND 1/64 GND VCC 1/96 VCC GND 1/128 VCC VCC
These terminals are valid only in the master mode. Connect them to V CC in the slave mode. STB TH CL1 CR, R, C 1 1 1 3 I VCC or GND Input terminal for testing Connect to STB V CC. Connect TH and CL1 to GND. Oscillator In the master mode, use these terminals as shown below:
Internal oscillation Rf R CR Cf C External clock Open R External clock CR Open C
In the slave mode, stop the oscillator as shown below: Open R
