High Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs

Data sheet acquired from Harris Semiconductor SCHS171 CD74HC257, CD74HCT257 High Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs Description The Harris CD74HC257 and CD74HCT257 are quad 2-input multiplexers which select four bits of data from two sources under the control of a common Select Input (S). The Output Enable input (OE) is active LOW. When OE is HIGH, all of the outputs (1Y-4Y) are in the high impedance state regardless of all other input conditions. Moving data from two groups of registers to four common output busses is a common use of the 257. The state of the Select input determines the particular register from which the data comes. It can also be used as a function generator. November 1997 Features • Buffered Inputs • Typical Propagation Delay ( In to Output ) = 12ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH [ /Title (CD74 HC257 , CD74 HCT25 7) /Subject (High Speed CMOS Logic Quad 2-Input Multiplexer Ordering Information PART NUMBER CD74HC257E CD74HCT257E CD74HC257M CD74HCT257M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC PKG. NO. E16.3 E16.3 M16.15 M16.15 Pinout CD74HC257, CD74HC257 (PDIP, SOIC) TOP VIEW S 1 1I0 2 1I1 3 1Y 4 2I0 5 2I1 6 2Y 7 GND 8 16 VCC 15 OE 14 4I0 13 4I1 12 4Y 11 3I0 10 3I1 9 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 File Number 1650.1 1 CD74HC257, CD74HCT257 Functional Diagram OE S 15 1 4I1 13 P N 12 4Y 4I0 14 3I1 3I0 2I1 2I0 1I1 1I0 10 11 6 5 3 2 3 CIRCUITS IDENTICAL TO CIRCUIT IN ABOVE DASHED ENCLOSURE 9 3Y 7 2Y 4 1Y TRUTH TABLE OUTPUT ENABLE OE H L L L L SELECT INPUT S X L L H H DATA INPUTS I0 X L H X X I1 X X X L H OUTPUT Y Z L H L H NOTE: H = High Voltage Level L = Low Voltage Level X = Don’t Care Z = High Impedance, OFF State 2 CD74HC257, CD74HCT257 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA Thermal Information Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 -0.02 -0.02 High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL -6 -7.8 0.02 0.02 0.02 Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND 6 7.8 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 V V V V V V V V V V V V V V V V µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS 3 CD74HC257, CD74HCT257 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Quiescent Device Current Three-State Leakage Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) Three-State Leakage Current NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ∆ICC VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC IOZ VI (V) VCC or GND VIL or VIH IO (mA) VCC (V) 0 6 6 MIN 25oC TYP MAX 8 ±0.5 -40oC TO 85oC MIN MAX 80 ±5 -55oC TO 125oC MIN MAX 160 ±10 UNITS µA µA -6 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V 0 0 - 5.5 5.5 4.5 to 5.5 - 100 ±0.1 8 360 - ±1 80 450 - ±1 160 490 µA µA µA IOZ VIL or VIH - 5.5 - - ±0.5 - ±5 - ±10 µA HCT Input Loading Table INPUT Data S OE UNIT LOADS 0.95 3 0.6 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 4 CD74HC257, CD74HCT257 Switching Specifications Input tr, tf = 6ns TEST CONDITIONS 25oC VCC (V) TYP MAX -40oC TO 85oC -55oC TO 125oC MAX MAX UNITS PARAMETER HC TYPES Propagation Delay In to Y SYMBOL tPLH, tPHL CL = 50pF 2 4.5 12 14 12 45 150 30 26 175 35 30 150 30 26 60 12 10 10 20 - 190 38 33 220 44 37 190 38 33 75 15 13 10 20 - 225 45 38 265 53 45 225 45 38 90 18 15 10 20 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF CL = 15pF CL = 50pF Propagation Delay S to Y tPLH, tPHL CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Propagation Delay OE to Y tPLZ, tPHZ, tPZL, tPZH CL = 50pF CL = 50pF CL = 15pF CL = 50pF Output Transition Times tTLH, tTHL CL = 50pF 5 6 2 4.5 5 6 2 4.5 6 Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 5, 6) HCT TYPES Propagation Delay In to Y Propagation Delay S to Y Propagation Delay OE to Y Output Transition Times Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 5, 6) NOTES: CI CO CPD - 5 tPLH, tPHL CL = 50pF CL = 15pF 4.5 5 4.5 5 4.5 5 4.5 5 13 12 16 45 33 38 30 12 10 20 - 41 48 38 15 10 20 - 50 57 45 18 10 20 - ns ns ns ns ns ns ns pF pF pF tPZL, tPZH CL = 50pF CL = 15pF tPLZ, tPHZ CL = 50pF CL = 15pF tTLH, tTHL CI CO CPD CL = 50pF - 5. CPD is used to determine the dynamic power consumption, per multiplexer. 6. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 5 CD74HC257, CD74HCT257 Test Circuits and Waveforms tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V GND tTHL INVERTING OUTPUT FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns OUTPUT DISABLE 90% 50% 10% tPZL 50% 10% tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 50% OUTPUTS DISABLED OUTPUTS ENABLED tPZH 6ns VCC GND FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tr OUTPUT DISABLE 6ns tf 2.7 1.3 tPLZ OUTPUT LOW TO OFF tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 6ns 3V 0.3 tPZL GND tPLZ OUTPUT LOW TO OFF 10% tPZH 1.3V 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make chan