Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

HC2509C March 1999 HC2509C Features l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs No External RC Network Required External Feedback (FBIN) Pin is Used to Synchronize the Outputs to the Clock Input Separate Output Enable for Each Output Bank Operates at 3.3 V Vcc 125 MHz Maximum Frequency On-chip Series Damping Resistors Support Spread Spectrum Clock(SSC) Synthesizers ESD Protection Exceeds 3000 V per MIL-STD883, Method 3015 ; Exceeds 350 V Using Machine Model ( C = 200 pF, R = 0 ) Latch-Up Performance Exceeds 400 mA per JESD 17 Packaged in Plastic 24-Pin Thin Shrink SmallOutline Package General Description The HC2509C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM. The HC2509C operates at 3.3V Vcc and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. The propagation delay from the CLK input to any clock output is nearly zero. One bank of five outputs and one bank of four outputs provide nine low-skew and low-jitter clocks. Each bank of outputs can be enabled or disabled separately via the control inputs (1G and 2G). Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The HC2509C is specially designed to interface with high speed SDRAM applications in the range of 25MHz to 125MHz and includes an internal RC network which provides excellent jitter characteristics and eliminates the needs for external components. For the test purpose, the PLL can be bypassed by strapping AVcc to ground. The HC2509C is characterized for operation from 0°C to 85°C. l l Pin Configuration TSSOP 24 PACKAGE (TOP VIEW) AGND Vcc 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 Vcc 1G FBOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK AVcc Vcc 2Y0 2Y1 GND Function Table INPUTS 1G 2G X L H L H CLK L H H H H 1Y (0:4) X L L H H L L L H H OUTPUTS 2Y (0:3) L L H L H L H H H H FBOUT GND 2Y2 2Y3 Vcc 2G FBIN 1 HC2509C March 1999 Functional Block Diagram 1G 11 3 1Y0 4 1Y1 5 1Y2 8 1Y3 9 1Y4 2G 14 21 2Y0 20 2Y1 17 CLK 24 16 PLL FBIN 13 12 23 2Y2 2Y3 FBOUT AVcc 2 HC2509C March 1999 Table 1. Pin Description Pin Name CLK FBIN IG 2G FBOUT 1Y(0:4) 2Y(0:3) Pin No. 24 13 11 14 12 3,4,5,8,9 16,17, 20,21 Type I I I I O O O Functional Description Clock Input. CLK provides the reference signal to the internal PLL. Feedback Input. FBIN provides the feedback signal to the internal PLL. Output Bank Enable. When 1G is high, all outputs 1Y(0:4) are enabled. When 1G is low, Outputs 1Y(0:4) are disabled to a logic-low state. Output Bank Enable. When 2G is high, all outputs 2Y(0:3) are enabled. When 2G is low, Outputs 2Y(0:3) are disabled to a logic-low state. Feedback Output. FBOUT completes the feedback loop of the PLL by being wired to FBIN. Clock Outputs. These outputs provide low-skew copies of CLKIN. Each output has an embedded series-damping resistor. Clock Outputs. These outputs provide low-skew copies of CLKIN. Each output has an embedded series-damping resistor. Analog Power Supply. AVcc provides the power reference for the analog circuitry. AVcc can be also used to bypass the PLL for the test purpose. When AVcc is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Analog Ground. AGND provides the ground reference for the analog circuitry. Power Supply Ground AVcc 23 Power AGND Vcc GND 1 2,10,15,22 6,7,18,19 Ground Power Ground Table 2. Absolute Maximum Ratings Over Operating Free-air Temperature Range Symbols Vcc VI Vo IIK IOK Io PMAX Tstg Parameter Supply Voltage Range Input Voltage Range Voltage Range applied to any input in the high or low state Input Clamp Current Output Clamp Current Continuous Output Current Maximum Power Dissipaiton Storage Temperature Range Value -0.5 to 4.6 -0.5 to 6.5 -0.5 to Vcc+0.5 ±50 ±50 ±50 0.7 -65 to 150 Unit V V V mA mA mA W °C Conditions VI <0 or VI >0 Vo<0 or Vo> Vcc Vo=0 to Vcc 3 HC2509C March 1999 Table 3. Recommended Operating Conditions Symbol AVcc Parameter Supply Voltage High-level Input Voltage Low-level Input Voltage Input Voltage High-level Output Current Low-level Output Current Operating Free-air Temperature Value Min Max 3 2 0 3.6 0.8 Vcc -12 12 85 Unit V V V V mA mA °C Condition VIH VIL VI IOH IOL TA 0 Table 4. Electrical Characteristics Over Recommended Operating Free-air Temperature Range Symbol VIK VOH Vcc - 0.2 2.1 2.4 0.2 0.8 0.55 ±5 10 500 4 6 Min Value Typ Max -1.2 Unit V V Vcc (V) 3 Min to Max 3 3 Min to Max 3 3 3.6 3.6 3.3 to 3.6 3.3 3.3 Test Conditions II = -18mA IOH = -100µA IOH = -12 mA IOH = -6 mA IOL = 100µA IOL = 12 mA IOL = 6 mA VI =Vcc or GND VI =Vcc or GND, Io = 0 Ouputs: low or high One input at Vcc - 0.6V, Other Inputs at Vcc or GND VI = Vcc or GND Vo = Vcc or GND VOL II ICC C Ci Co V µA µA µA pF pF Table 5.Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-air Temperature Symbol fclock Parameter Clock Frequency Input Clock Duty Cycle Stabilization Time♣ Value Min 25 40 Max 125 60 1 Unit MHz % ms ♣ Time to obtain phase lock of its feedback signal to its reference signal. 4 HC2509C March 1999 Table 6. Switching Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-air Temperature.(CL=30pF) (see Figure1 and 2) = Parameter tphase error ♣ (normalized) From(Input) 66MHz < CLKIN↑< 100MHz CLKIN↑ = 100MHz Any Y of FBOUT CLKIN > 66MHz CLKIN > 66MHz TO(Output) FBIN↑ FBIN↑ Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Vcc = 3.3V ±0.165V Min Typ Max -150 -50 -150 50 Vcc = 3.3V±0.3V Unit Min Typ Max ps ps 200 -100 45 100 55 2.1 2.7 ps ps % ns ns tsk Jitter(pk-pk) Duty Cycle tr tf 1.3 1.7 1.9 2.5 0.8 1.2 =These parameters are not production tested. ♣ Phase error does not include jitter. Figure 1. Load Circuit and Voltage Waveforms 3V From Output Under Test Input 50% Vcc 0V tpd 30pF 500§Ù VOH 2V 2V 0.4V 50% Vcc 0.4V Output tr tf VOL Load Circuit For Outputs Voltage Waveforms Propagation Delay Times Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz, Zo =50Ω, tr =1.2ns, tf=1.2ns 2.The outputs are measured one at a time with one transition per measurement. 5 HC2509C March 1999 Figure 2. Phase Error and Skew Calculations CLKIN FBIN t phase error Any Y Any Y tSK FBOUT Any Y tSK 6