(GS8662RxxE-xxx) 72Mb SigmaCIO DDR-II Burst of 4 SRAM

www.DataSheet4U.com Preliminary GS8662R08/09/18/36E-333/300/250/200/167 165-Bump BGA Commercial Temp Industrial Temp Features 72Mb SigmaCIO DDR-II Burst of 4 SRAM 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O • Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 4 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with present 9Mb, 18Mb, 36Mb and future 144Mb devices • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available Bottom View 165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs always transfer data in four packets. When a new address is loaded, A0 and A1 preset an internal 2 bit linear address counter. The counter increments by 1 for each beat of a burst of four data transfer. The counter always wraps to 00 after reaching 11, no matter where it starts. Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer data in four packets. When a new address is loaded, the LSBs are internally set to 0 for the first read or write transfer, and incremented by 1 for the next 3 transfers. Because the LSBs are tied off internally, the address field of a x8 SigmaCIO DDR-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 4M x 18 has a 1024K addressable index). SigmaCIO™ Family Overview The GS8662R08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662R08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS8662R08/09/18/36E SigmaCIO DDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended Parameter Synopsis -333 tKHKH tKHQV 3.0 ns 0.45 ns -300 3.3 ns 0.45 ns -250 4.0 ns 0.45 ns -200 5.0 ns 0.45 ns -167 6.0 ns 0.5 ns Rev: 1.01 9/2005 1/37 © 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS8662R08/09/18/36E-333/300/250/200/167 2M x 36 SigmaCIO DDR-II SRAM—Top View 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 MCL/SA (144Mb) DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 SA DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA1 VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to DQ27:DQ35 2. MCL = Must Connect Low Rev: 1.01 9/2005 2/37 © 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS8662R08/09/18/36E-333/300/250/200/167 4M x 18 SigmaCIO DDR-II SRAM—Top View 1 2 SA DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 SA NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA1 VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17 2. MCL = Must Connect Low Rev: 1.01 9/2005 3/37 © 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS8662R08/09/18/36E-333/300/250/200/167 8M x 9 SigmaCIO DDR-II SRAM—Top View 1 2 SA NC NC NC NC NC NC VREF NC NC DQ7 NC NC NC TCK 3 SA NC NC NC DQ5 NC DQ6 VDDQ NC NC NC NC NC DQ8 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC NC NC NC VREF DQ2 NC NC NC NC NC TMS 11 CQ DQ4 NC NC DQ3 NC NC ZQ NC NC DQ1 NC NC DQ0 TDI A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to 0 at the beginning of each access. 2. MCL = Must Connect Low Rev: 1.01 9/2005 4/37 © 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS8662R08/09/18/36E-333/300/250/200/167 8M x 8 SigmaCIO DDR-II SRAM—Top View 1 2 SA NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 SA NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC NW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC NC TDI A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to 0 at the beginning of each access. 2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7 3. MCL = Must Connect Low Rev: 1.01 9/2005 5/37 © 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS8662R08/09/18/36E-333/300/250/200/167 Pin Description Table Symbol SA NC R W BW0–BW3 NW0–NW1 LD K K C C TMS TDI TCK TDO VREF ZQ MCL DQ Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die or any other pin Description Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Writes Nybble Write Control Pin Synchronous Load Pin Input Clock Input Clock Output Clock Output Clock Test Mode Select Test Data Input Test Clock Input Test Data Output HSTL Input Reference Voltage Output Impedance Matching Input Must Connect Low Data I/O Disable DLL when low Output Echo Clock Output Echo Clock Power Supply Isolated Output Buffer Supply Power Supply: Ground Type Input — Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input — Input/Output Input Output Output Supply Supply Supply Comments — — Active High Active Low Active Low x18/x36 only Active Low x8 only Active Low Active High Active Low Active High Active Low — — — — — — — Three State Active Low — — 1.8 V Nominal 1.5 V Nominal — Rev: 1.01 9/2005 6/37 © 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS8662R08/09/18/36E-333/300/250/200/167 Background Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications. Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half. Burst Operations Read and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated in the timing diagrams. It is not possible to stop a burst once it starts. Four beats of data are always transferred. This means that it is possible to load new address