(GS8642xxB/C-xxxV) 4M x 18 / 2M x 36/ 1M x 72 72Mb S/DCD Sync Burst SRAMs

www.DataSheet4U.com Preliminary GS864218/36/72(B/C)-xxxV 119- & 209-Pin BGA Commercial Temp Industrial Temp Features 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs 250 MHz–167 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O • FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable • IEEE 1149.1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 119- and 209-bump BGA package • RoHS-compliant 119- and 209-bump BGA packages available Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. SCD and DCD Pipelined Reads The GS864218/36/72(B/C)-xxxV is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. FLXDrive™ The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Core and Interface Voltages The GS864218/36/72(B/C)-xxxV operates on a 1.8 V or 2.5 V power supply. All inputs are 1.8 V or 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V or 2.5 V compatible. Functional Description Applications The GS864218/36/72(B/C)-xxxV is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Parameter Synopsis -250 Pipeline 3-1-1-1 tKQ) tCycle Curr (x18) Curr (x36) Curr (x72) tKQ tCycle Curr (x18) Curr (x36) Curr (x72) 3.0 4.0 340 410 520 6.5 6.5 245 280 370 -200 3.0 5.0 290 350 435 7.5 7.5 220 250 315 -167 3.5 6.0 260 305 380 8.0 8.0 210 240 300 Unit ns ns mA mA mA ns ns mA mA mA Flow Through 2-1-1-1 Rev: 1.03 6/2006 1/35 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864218/36/72(B/C)-xxxV 209-Bump BGA—x72 Common I/O—Top View (Package C) 1 A B C D E F G H J K L M N P R T U V W DQG DQG DQG DQG DQPG DQC DQC DQC DQC NC DQH DQH DQH DQH DQPD DQD DQD DQD DQD 2 DQG DQG DQG DQG DQPC DQC DQC DQC DQC NC DQH DQH DQH DQH DQPH DQD DQD DQD DQD 3 A BC BH VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS A A TMS 4 E2 BG BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 ADSP NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 6 ADSC BW E1 G VDD ZQ MCH MCL MCL MCL FT MCL SCD ZZ VDD LBO A A1 A0 7 ADV A NC GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 8 E3 BB BE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A BF BA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A A TCK 10 DQB DQB DQB DQB DQPF DQF DQF DQF DQF NC DQA DQA DQA DQA DQPA DQE DQE DQE DQE 11 DQB DQB DQB DQB DQPB DQF DQF DQF DQF NC DQA DQA DQA DQA DQPE DQE DQE DQE DQE A B C D E F G H J K L M N P R T U V W 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Rev: 1.03 6/2006 2/35 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864218/36/72(B/C)-xxxV GS864272C-xxxV 209-Bump BGA Pin Description Symbol A0, A1 An DQA DQB DQC DQD DQE DQF DQG DQH BA, BB BC,BD BE, BF, BG,BH NC CK GW E1 E3 E2 G ADV ADSP, ADSC ZZ FT LBO SCD MCH MCL BW ZQ TMS TDI TDO TCK I I I I O I Type I I Description Address field LSBs and Address Counter Preset Inputs. Address Inputs I/O Data Input and Output pins I I I — I I I I I I I I I I I I I Byte Write Enable for DQA, DQB I/Os; active low Byte Write Enable for DQC, DQD I/Os; active low Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Single Cycle Deselect/Dual Cycle Deselect Mode Control Must Connect High Must Connect Low Byte Enable; active low FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Rev: 1.03 6/2006 3/35 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864218/36/72(B/C)-xxxV GS864272C-xxxV 209-Bump BGA Pin Description (Continued) Symbol VDD VSS VDDQ Type I I I Description Core power supply I/O and Core Ground Output driver power supply Rev: 1.03 6/2006 4/35 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864218/36/72(B/C)-xxxV 119-Bump BGA—x36 Common I/O—Top View (Package B) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC2 DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A A A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A A TMS 3 A A A VSS VSS VSS BC VSS NC VSS BD VSS VSS VSS LBO A TDI 4 ADSP ADSC VDD ZQ E1 G ADV GW VDD CK SCD BW A1 A0 VDD A TCK 5 A A A VSS VSS VSS BB VSS NC VSS BA VSS VSS VSS FT A TDO 6 A A A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A A NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ A B C D E F G H J K L M N P R T U 7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch Rev: 1.03 6/2006 5/35 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864218/36/72(B/C)-xxxV 119-Bump BGA—x18 Common I/O—Top View (Package B) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC A VDDQ 2 A A A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A TMS 3 A A A VSS VSS VSS BB VSS NC VSS NC VSS VSS VSS LBO A TDI 4 ADSP ADSC VDD ZQ E1 G ADV GW VDD CK SCD BW A1 A0 VDD A TCK 5 A A A VSS VSS VSS NC VSS NC VSS BA VSS VSS VSS FT A TDO 6 A A A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ A B C D E F G H J K L M N P R T U 7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch Rev: 1.03 6/2006 6/35 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864218/36/72(B/C)-xxxV GS864218/36B-xxxV 119-Bump BGA Pin Description Symbol A0, A1 An DQA DQB DQC DQD BA, BB, BC, BD NC CK BW GW E1 G ADV ADSP, ADSC ZZ FT LBO ZQ SCD TMS TDI TDO TCK VDD VSS VSS VDDQ Type I I I/O I — I I I I I I I I I I I I I I O I I I I I Description Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low No Connect Clock Input Signal; active high Byte Write—Writes all enabled bytes; active low Global Write Enable—Writes all bytes; active low Chip Enable; active low Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low FLXDrive Output Impedance Control (Low = Low Impedance [High