Description
www.DataSheet4U.com Preliminary GS864018/32/36T-xxxV 100-Pin TQFP Commercial Temp Industrial Temp Features 4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs 250 MHz–167 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package • RoHS-compliant 100-lead TQFP package available cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS864018/32/36T-xxxV operates on a 1.8 V or 2.5 V power supply. All inputs are 1.8 V or 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V or 2.5 V compatible. Functional Description Applications The GS864018/32/36T-xxxV is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst Parameter Synopsis tKQ tCycle Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36) -250 2.5 4.0 340 410 6.5 6.5 245 280 -200 3.0 5.0 290 350 7.5 7.5 220 250 -167 3.5 6.0 260 305 8.0 8.0 210 240 Unit ns ns mA mA ns ns mA mA Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.01 6/2006 1/23 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864018/32/36T-xxxV GS864018T-xxxV 100-Pin TQFP Pinout (Package T) VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 4M x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Rev: 1.01 6/2006 LBO A A A A A1 A0 A A VSS VDD A A A A A A A A A 2/23 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864018/32/36T-xxxV GS864032T-xxxV 100-Pin TQFP Pinout (Package T) NC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 2M x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC Rev: 1.01 6/2006 LBO A A A A A1 A0 A A VSS VDD A A A A A A A A A 3/23 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864018/32/36T-xxxV GS864036T-xxxV 100-Pin TQFP Pinout (Package T) DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC3 VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 2M x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA Rev: 1.01 6/2006 LBO A A A A A1 A0 A A VSS VDD A A A A A A A A A 4/23 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864018/32/36T-xxxV TQFP Pin Description Symbol A 0, A 1 A DQA DQB DQC DQD NC BW BA , BB BC , BD CK GW E 1, E 3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ I I I I I I I I I I I I I I I I Type I I I/O Description Address field LSBs and Address Counter preset Inputs Address Inputs Data Input and Output pins No Connect Byte Write—Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low Clock Input Signal; active high Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply Rev: 1.01 6/2006 5/23 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864018/32/36T-xxxV GS864018/32/36T-xxxV Block Diagram A0–An Register D Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1 A LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q D Register D BB Q 36 4 36 Register D BC Q Q Register D Register Q Register D D BD Q Register D Q E1 E2 E3 Register D Q Register D Q FT G Power Down Control ZZ SCD DQx1–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.01 6/2006 6/23 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864018/32/36T-xxxV Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Pin Name LBO FT ZZ State L H L H or NC L or NC H Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table. Burst Counter Sequences Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.01 6/2006 7/23 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. www.DataSheet4U.com Preliminary GS864018/32/36T-xxxV Byte Write Truth Table Function Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes GW H H H H H H H BW H L L L L L L BA X H L H H H L BB X H H L H H L BC X H H H L H L BD X H H H H L L Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.01 6/2006 8/23 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnolo

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