256K X16 4Mb Asynchronous SRAM

GS74116ATP/J/X SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp Features • Fast access time: 8, 10, 12 ns • CMOS low power operation: 130/105/95 mA at minimum cycle time • Single 3.3 V power supply • All inputs and outputs are TTL-compatible • Byte control • Fully static operation • Industrial Temperature Option: –40° to 85°C • Package line up J: 400 mil, 44-pin SOJ package GJ: RoHS-compliant 400 mil, 44-pin SOJ package TP: 400 mil, 44-pin TSOP Type II package GP: RoHS-compliant 400 mil, 44-pin TSOP Type II package X: 6 mm x 10 mm Fine Pitch Ball Grid Array package GX: RoHS-compliant 6 mm x 10 mm Fine Pitch Ball Grid Array package • RoHS-compliant SOJ, TSOP-II, and FP-BGA packages available 256K x 16 4Mb Asynchronous SRAM Pin Descriptions Symbol A0–A17 DQ1–DQ16 CE LB UB WE OE VDD VSS NC 8, 10, 12 ns 3.3 V VDD Center VDD and VSS Description Address input Data input/output Chip enable input Lower byte enable input (DQ1 to DQ8) Upper byte enable input (DQ9 to DQ16) Write enable input Output enable input +3.3 V power supply Ground No connect Description The GS74116A is a high speed CMOS Static RAM organized as 262,144 words by 16 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS74116A is available in a 6 x 10 mm Fine Pitch BGA package, 400 mil SOJ and 400 mil TSOP Type-II packages. SOJ 256K x 16-Pin Configuration (Package J) A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 A17 Top view 44-pin SOJ Rev: 1.07 11/2005 1/16 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X FP-BGA 256K x 16 Bump Configuration (Package X) 1 2 3 4 5 6 A B C D E F G H LB DQ16 OE UB A0 A3 A5 A17 NC A8 A10 A13 A1 A4 A6 A7 A16 A9 A11 A14 A2 CE DQ2 DQ4 DQ5 DQ7 WE A15 NC DQ1 DQ3 VDD VSS DQ6 DQ8 NC DQ14 DQ15 VSS VDD DQ13 DQ12 DQ11 DQ10 DQ9 NC NC A12 6 x 10 mm Bump Pitch Top View TSOP-II 256K x 16 Pin Configuration (Package TP) A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 A17 Top view 44 pin TSOP II Rev: 1.07 11/2005 2/16 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X Block Diagram A0 Address Input Buffer Row Decoder Memory Array A17 CE WE Control OE UB _____ Column Decoder I/O Buffer DQ1 DQ16 Truth Table CE H OE X WE X LB X L UB X L H L L H L X H DQ1 to DQ8 Not Selected Read Read High Z Write Write Not Write, High Z High Z High Z DQ9 to DQ16 Not Selected Read High Z Read Write Not Write, High Z Write High Z High Z VDD Current ISB1, ISB2 L L H L H L L X L L H IDD L L Note: X: “H” or “L” H X H X X H Rev: 1.07 11/2005 3/16 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature Symbol VDD VIN VOUT PD TSTG Rating –0.5 to +4.6 –0.5 to VDD +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) 0.7 –55 to 150 Unit V V V W oC Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Recommended Operating Conditions Parameter Supply Voltage for -8/-10/-12 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range Symbol VDD VIH VIL TAc TAI Min 3.0 2.0 –0.3 0 –40 Typ 3.3 — — — — Max 3.6 VDD +0.3 0.8 70 85 Unit V V V o C C o Notes: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns. Capacitance Parameter Input Capacitance Output Capacitance Symbol CIN COUT Test Condition VIN = 0 V VOUT = 0 V Max 5 7 Unit pF pF Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested. Rev: 1.07 11/2005 4/16 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X DC I/O Pin Characteristics Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol IIL ILO VOH VOL Test Conditions VIN = 0 to VDD Output High Z VOUT = 0 to VDD IOH = –4 mA ILO = +4 mA Min – 1 uA –1 uA 2.4 — Max 1 uA 1 uA — 0.4 V Power Supply Currents Parameter Symbol Test Conditions CE ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA CE ≥ VIH All other inputs ≥ VIH or ≤ VIL Min. cycle time CE ≥ VDD – 0.2V All other inputs ≥ VDD – 0.2 V or ≤ 0.2 V 0 to 70°C 8 ns 10 ns 12 ns 8 ns –40 to 85°C 10 ns 12 ns Unit Operating Supply Current IDD 130 105 90 140 115 100 mA Standby Current ISB1 30 25 25 40 35 35 mA Standby Current ISB2 10 20 mA Rev: 1.07 11/2005 5/16 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X AC Test Conditions Parameter Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load Conditions VIH = 2.4 V VIL = 0.4 V tr = 1 V/ns tf = 1 V/ns 1.4 V 1.4 V Fig. 1& 2 Output Load 1 DQ 50Ω VT = 1.4 V 30pF1 Output Load 2 3.3 V DQ 5pF1 589Ω 434Ω Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ Rev: 1.07 11/2005 6/16 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X AC Characteristics Read Cycle Parameter Read cycle time Address access time Chip enable access time (CE) Byte enable access time (UB, LB) Output enable to output valid (OE) Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Byte enable to output in low Z (UB, LB) Chip disable to output in High Z (CE) Output disable to output in High Z (OE) Byte disable to output in High Z (UB, LB) * These parameters are sampled and are not 100% tested. Symbol tRC tAA tAC tAB tOE tOH tLZ* tOLZ* tBLZ* tHZ* tOHZ* tBHZ* -8 Min 8 — — — — 3 3 0 0 — — — Max — 8 8 3.5 3.5 — — — — 4 3.5 3.5 Min 10 — — — — 3 3 0 0 — — — -10 Max — 10 10 4 4 — — — — 5 4 4 Min 12 — — — — 3 3 0 0 — — — -12 Max — 12 12 5 5 — — — — 6 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL tRC Address tAA tOH Data Out Previous Data Data valid Rev: 1.07 11/2005 7/16 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X Read Cycle 2: WE = VIH tRC Address tAA CE tAC tLZ UB, LB OE tBLZ tOE Data Out tOLZ High impedance tAB tBHZ tOHZ Data valid tHZ Write Cycle Parameter Write cycle time Address valid to end of write Chip enable to end of write Byte enable to end of write Data set up time Data hold time Write pulse width Address set up time Write recovery time (WE) Write recovery time (CE) Output Low Z from end of write Write to output in High Z Symbol tWC tAW tCW tBW tDW tDH tWP tAS tWR tWR1 tWLZ* tWHZ* -8 Min 8 5.5 5.5 5.5 4 0 5.5 0 0 0 3 — Max — — — — — — — — — — — 3.5 Min 10 7 7 7 4.5 0 7 0 0 0 3 — -10 Max — — — — — — — — — — — 4 Min 12 8 8 8 6 0 8 0 0 0 3 — -12 Max — — — — — — — — — — — 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns * These parameters are sampled and are not 100% tested. Rev: 1.07 11/2005 8/16 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X Write Cycle 1: WE control tWC Address tAW OE tCW CE tBW UB, LB tAS WE tDW Data In tWHZ Data Out tDH Data valid tWLZ High impedance tWP tWR Write Cycle 2: CE control tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data In Data Out tDH Data valid tCW tWR1 High impedance Rev: 1.07 11/2005 9/16 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X Write Cycle 3: UB, LB control tWC Address tAW OE tAS CE tBW UB, LB tWP WE tDW Data In Data Out tDH Data valid tCW tWR1 High impedance Rev: 1.07 11/2005 10/16 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X 44-Pin, 400 mil SOJ Symbol A A1 A2 HE GE E B B1 1 e 22 A D 44 23 L c Dimension in inch min nom max — 0.025 0.105 — 0.026 — 1.120 0.395 — 0.435 0.360 0.082 — 0 o Dimension in mm min nom max — 0.635 2.667 — 0.660 — 28.44 10.033 — 11.049 9.144 2.083 — 0 o — — 0.110 0.018 0.028 0.008 1.125 0.400 0.05 0.440 0.370 0.087 — — 0.148 — 0.115 — 0.032 — 1.130 0.405 — 0.445 0.380 0.1